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Week In Review: Design, Low Power


Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Design, Low Power


Memory CEA-Leti demonstrated 16-kbit ferroelectric random-access memory (FeRAM) arrays at the 130nm node. It utilizes back-end-of-line (BEOL) integration of TiN/HfO2:Si/TiN ferroelectric capacitors as small as 0.16 µm² and solder reflow compatibility for the first time for this type of memory. The researchers anticipate it will be useful for embedded applications such at IoT and wearable dev... » read more

Week In Review: Design, Low Power


Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Week In Review: Design, Low Power


Synopsys acquired Qualtera, a provider of big data analytics for semiconductor test and manufacturing. Based in Montpellier, France and founded in 2010, Qualtera's Silicondash platform provides both off-line and in-line modules for data analytics, visualization, simulation, and modeling to allow for development of control strategies. Combined with Synopsys' TestMAX test automation solution, the... » read more

Week In Review: Design, Low Power


Tools & IP Ansys' RedHawk-SC multiphysics signoff software was certified for all TSMC advanced process technologies, including N16, N12, N7, N6 and N5. The certification includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis and statistical EM budgeting analysis. Aldec launched a new FPGA accelerator board for high performance... » read more

Week In Review: Design, Low Power


Aldec launched the HES-MPF500-M2S150 Development Kit for early co-development and co-verification of hardware and software for FPGA-based embedded systems that will use devices from either or both of Microchip’s PolarFire or SmartFusion2 families. The HES-MPF500-M2S150 Development Kit features Microchip’s low power PolarFire MPF500T FCG1152 FPGA, which has 481k logic elements, 1480 math blo... » read more