Week In Review: Design, Low Power

Aldec launched the HES-MPF500-M2S150 Development Kit for early co-development and co-verification of hardware and software for FPGA-based embedded systems that will use devices from either or both of Microchip’s PolarFire or SmartFusion2 families. The HES-MPF500-M2S150 Development Kit features Microchip’s low power PolarFire MPF500T FCG1152 FPGA, which has 481k logic elements, 1480 math blocks, 33Mbits of RAM, and 584 I/Os, along with the SmartFusion2 M2S150 FPGA, with embedded Arm Cortex-M3 microcontroller subsystem with DDR3 memory controllers. The two FPGAs are connected via direct I/Os and both devices have access, via a PCIe switch, to a PCIe x4 Gen2 Edge Connector; this switch that allows the FPGAs to work together or independently.

S2C debuted its new S10 10M Prodigy Logic System family of FPGA prototyping devices based on Intel Stratix 10 GX 10M FPGA which will be available in Single, Dual and Quad FPGA configurations. The Single S10 10M Prodigy Logic System is shipping immediately and supports up to 1.4 Gbps for general-purpose I/O, and up to 17.4 Gbps for the high-speed transceivers. Remote management capabilities are supported over USB or Ethernet, including FPGA configuration, power on/off/recycle, Virtue UART for debugging, system monitoring, as well as identification of the presence of specific Prodigy daughter cards, and remote test with the auto-detection technology.

Imperas updated the RISC-V compliance test suite for RV32I base RISC-V configuration to provide almost 100% functional coverage of the instructions. The compliance suite is available from the RISC-V Foundation GitHub repository for the compliance task group. Imperas also updated its free RISC-V Open Virtual Platform Simulator (riscvOVPsim) as a reference Instruction Set Simulator for users and developers of the compliance suite.

Silex Insight added two new Video Codec IPs using RAW input from Bayer filter (CFA) to its codec lineup. The company says RAW Bayer data is an effective way of capturing color information as it has a substantial reduction in file data compared to the full raster RGB/YUV equivalent (uncompressed), and targets a large range of image sensor applications from machine vision, drones and mobile, to professional cameras. The codec IP comes in 2 different variants, JPEG 2000 as a robust high quality video codec and VC-2 HQ as a lightweight slice-based video codec. They can handle any resolutions, including 24K sensor, supporting sensors with 16bits and a user defined compression ratio.

Events
Check out upcoming industry events and conferences: Accellera will hold a Proposed Working Group meeting on a potential standard for FMEDA tool interoperability on Dec. 6 at NXP in Munich, Germany. The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA. Next year, DesignCon will take place January 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design.