Clock Domain Crossings in the FPGA World


Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Week In Review: Design, Low Power


M&A Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic's tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company's technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. Th... » read more

Week In Review: Design, Low Power


M&A Rambus acquired the assets of Diablo Technologies. Founded in 2003, Diablo Technologies specialized in NVDIMM technologies, but was hit with a patent lawsuit by Netlist in 2013. While Diablo won the lawsuit and several subsequent appeals, it declared bankruptcy in December 2017. Rambus says the technology will provide a foundation for integrating existing DRAM and Flash along with emer... » read more

Deep Learning Hardware: FPGA vs. GPU


FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer a HW platform that runs computationally intensive machine learning algorithms fast and efficiently. As Deep Learning has driven most of the advanced machine learning applications, it is r... » read more

DO-254 Solutions Blueprint


The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL simulator, synthesis, place & route and static timing analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including requirements management, traceability, tests management, de... » read more

Resets and Reset Domain Crossings in ASIC and FPGA designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To read more, click here. » read more

Week In Review: Design, Low Power


Tools & Standards Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout... » read more

The Impact of Domain Crossing on Safety


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Linting With ALINT-PRO Within Active-HDL


Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

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