The Week In Review: Design


Tools Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include improved performance when using code containing many inline randomized calls and up to 29% faster simulation speed of UVM. Pulsic added new features to its Unity Bus Planner for planning... » read more

The Week In Review: Design


M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

Inside UVM


We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount of the verification effort needed for this type of SoC - the required manpower and time to get the job done is absolutely mind-boggling. Thankfully, we have several pre... » read more

Dealing With Deadlocks


Deadlocks are becoming increasingly problematic as designs becoming more complex and heterogeneous. Rather than just integrating IP, the challenge is understanding all of the possible interactions and dependencies. That affects the choice of IP, how it is implemented in a design, and how it is verified. And it adds a whole bunch of unknowns into an already complex formula for return on inves... » read more

Starting Point Is Changing For Designs


The starting point for semiconductor designs is shifting. What used to be a fairly straightforward exercise of choosing a processor based on power or performance, followed by how much on-chip versus off-chip memory is required, has become much more complicated. This is partly due to an emphasis on application-specific hardware and software solutions for markets that either never existed befo... » read more

Blog Review: Oct. 4


Synopsys' Prishkrit Abrol digs into how USB Type-C Alternate Mode allows MHL, DisplayPort, HDMI, and Thunderbolt over cable. Mentor's Paul Morrison dives into how hardware emulation can help verify the complexities of new storage devices. Cadence's Madhavi Rao listens in as Somshubhro Pal Choudhury of Bharat Innovations describes the IoT stack, hype cycle, and why it's happening now. R... » read more

Prototypes Proliferate


Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

Finite State Machine Synthesis In Programmable Circuits


Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions? For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology. C... » read more

Synthesis Of Energy-Efficient FSMs Implemented In PLD Circuits


The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous ci... » read more

Blog Review: Sept. 20


Mentor's Jeff Miller warns that MEMS accelerometers are vulnerable to takeover using specially constructed sound waves, as demonstrated in a new paper. Synopsys' Pooja Gupta and Srinivas Vijayaragavan explain some major technology updates in SAS 24G with a look at Binary primitives, Extended Binary primitives and primitive parameters. Cadence's Paul McLellan shares highlights from TSMC's ... » read more

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