Resets and Reset Domain Crossings in ASIC and FPGA designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To read more, click here. » read more

Week In Review: Design, Low Power


Tools & Standards Mentor uncorked a PCB design platform for non-specialist PCB engineers focused on multi-dimensional verification. The Xpedition platform can integrate a range of verification tools within a singular authoring environment, providing automatic model creation, concurrent simulation, cross probing from results, and error reviews to identify problems at the schematic or layout... » read more

The Impact of Domain Crossing on Safety


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Linting With ALINT-PRO Within Active-HDL


Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

So Many Waivers Hiding Issues


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Giving Cars A Bird’s-Eye View


Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable of human transportation was built in 1769 [1]! As a person who likes driving, I wouldn’t like to have a ‘fully’ autonomous car, but I would like to get some assistanc... » read more

Domain Crossing Nightmares


Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Accessing Registers With UVM-RAL


As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register can have several fields within it and each field can represent a particular feature that can be configured. The device then reads that register and uses that information to change settings or modes... » read more

Debug Issues Grow At New Nodes


Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

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