Author's Latest Posts


HDL Simulation Acceleration Solution For Microchip FPGA Designs


Mission-critical FPGA designs for space and radar applications continue to increase in complexity, such that they require a comprehensive and robust verification environment. There are hardware-in-the-loop solutions in the market that utilize FPGA boards, but when it comes to establishing functional coverage and debugging the custom logic, users would typically need to go back to HDL simulation... » read more

Clarifying Language/Methodology Confusion


Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

DO-254 Requirements Traceability


DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. This paper explains the rationale behind requirements traceability including its purpose and resulting benefits when done correctly. Click here to re... » read more

Clock Domain Crossings in the FPGA World


Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

DO-254 Solutions Blueprint


The Federal Aviation Administration (FAA) recognizes the use of commonly used tools for FPGA design and verification such as RTL simulator, synthesis, place & route and static timing analysis. For DAL A and B FPGAs, the FAA also recognizes other tools that improve design, verification, traceability and project management including requirements management, traceability, tests management, de... » read more

Resets and Reset Domain Crossings in ASIC and FPGA designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To read more, click here. » read more

Linting With ALINT-PRO Within Active-HDL


Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

DO-254: Increasing Verification Coverage By Test


Verification coverage by test is essential to satisfying both the objectives of DO-254 and interpretation in FAA Oder 8110.105. However, verification of requirements by test during final board testing is challenging and time-consuming in most cases. This white paper explains the reasons behind these challenges and provides recommendations for how to overcome them. The recommendations center ... » read more

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