Author's Latest Posts


Resets and Reset Domain Crossings in ASIC and FPGA designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To read more, click here. » read more

Linting With ALINT-PRO Within Active-HDL


Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level linting and unit linting. Both methods complement each other and are usually applied at different stages of the design cycle. Unit linting is a relatively new approach that is well combinable with... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs


This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

DO-254: Increasing Verification Coverage By Test


Verification coverage by test is essential to satisfying both the objectives of DO-254 and interpretation in FAA Oder 8110.105. However, verification of requirements by test during final board testing is challenging and time-consuming in most cases. This white paper explains the reasons behind these challenges and provides recommendations for how to overcome them. The recommendations center ... » read more

Partitioning Challenges In Multi-FPGA Prototyping


Multi-FPGA prototyping of ASIC & SoC designs enables the highest clock rates among emulation techniques. However, design setup for prototyping is much more complicated and challenging. In this White Paper we uncover the common challenges of partitioning design to multiple FPGAs and provide solutions that will improve your prototype quality and shorten time spent on design setup. To read ... » read more

Achieving RTL-To-Netlist Equivalence


Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

Synthesis Of Energy-Efficient FSMs Implemented In PLD Circuits


The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous ci... » read more

Building And Configuring A Linux OS From Linaro


The Linux operating system is a very popular operating system for embedded applications. Many modern systems including IoT gateways use the Linux OS because of its versatility and support for multiple architectures. The Aldec TySOM platform, which is based on the Xilinx Zynq SoC with ARM Cortex processor, can be utilized as an IoT Gateway system. This document describes the process for building... » read more

FPGA VHDL Verification


By Espen Tallaksen This is actually possible – and with an average efficiency improvement of 20% to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost. All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good to... » read more

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