Week In Review: Design, Low Power

ML for implementation flows; 3nm power analytics; ASIC/SoC physical prototyping; ReRAM PUFs.


Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow for many blocks concurrently. Renesas and Samsung Foundry noted using Cerebrus.

Ansys announced enhancements in the latest release of its tool suite, Ansys 2021 R2. In semiconductors, 2021 R2 provides 3nm-ready Advanced Power Analytics (APA) and improves voltage-drop fixing efficiency by 3X, using aggressor identification, what-if analysis, and links to engineering change order (ECO) tools. Ansys said that 2021 R2 improves cost and core-hour efficiency by 4X when using cloud for semiconductor simulation. Additionally, the new Phi Plus mesher speeds initial meshing for bondwire package electromagnetics and signal integrity analysis by an average of 6-10x. Also available are new Chip-Package-System and PCB enhanced workflows with automation for IC-on-Package and Multi-Zone PCBs with rigid flex cables.

Aldec launched an ASIC/SoC physical prototyping and hardware emulation board that can accommodate designs of about 83M ASIC gates in size. HES-VU19PD-ZU7EV uses only two FPGAs for provision of logic to simplify partitioning. For larger designs, four boards can be connected. The logic module FPGAs are both Virtex UltraScale+ VU19P devices and it also includes a Zynq UltraScale+ ZU7EV MPSoC as host module. It also includes a PCIe Switch device which provides PCIe x16 Gen 3 connections with the logic devices and PCIe x8 Gen 3 connections with the controller FPGA.

Imperas Software updated its riscvOVPsimPlus free reference model with support for the near ratified RISC-V P extension and architectural validation test suites. The P (or Packed SIMD/DSP) extension supports real-time data processing applications as part of the main processor pipeline without the need for a co-processor. riscvOVPsimPlus is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions and includes several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions.

Synopsys’ VC Functional Safety Manager, which provides automation for the functional safety Failure Mode Effects Analysis (FMEA) and Failure Modes Effects Diagnostic Analysis (FMEDA) for automotive SoCs, received new features as part of a collaboration with Samsung Foundry. It now supports top-down flow and what-if analysis for early safety architecture exploration, quick synthesis for RTL design data extraction, support for application lifecycle management tools, and handling failure modes and fault injection in analog parts of the SoC.

Ansys Power Library (APL), a tool for characterizing design libraries and calculating chip power and reliability, is now available for the Arm Neoverse architecture to support development on AWS Graviton2 processors.

Gowin Semiconductor released an image signal processor (ISP) IP portfolio and reference design for its FPGAs. Targeting affordable camera products, the ISP IP takes pixel data from an image sensor and adjusts it through CFA (Color Filter Array/Debayer), CCM (Color Correction Array), Gamma correction, and AE (Auto Exposure) and AWB (Auto White Balance) to provide a balanced image. It 8bit/10bit image data and provides an adjustable register map for different image sensors and resolutions.

CEVA’s RivieraWaves Bluetooth 5.3 IP is now available as a complete hardware/software solution for new designs and as a software-only upgrade for compatible existing designs. Improvements in Bluetooth 5.3 include increased protocol efficiency, link robustness, and wireless security.

Infineon launched high-density radiation-tolerant (RadTol) NOR Flash memory products for space-grade FPGAs. The 256 Mb and 512 Mb NOR Flash is qualified to MIL-PRF-38535’s QML-V flow, the highest quality and reliability standard certification for aerospace-grade ICs and targets applications such as FPGA configuration, image storage, microcontroller data and boot code storage. The devices are radiation-tolerant up to 30 krad (Si) biased and 125 krad (Si) unbiased. At 125°C, the devices support 1,000 Program/Erase cycles and 30 years of data retention and at 85°C 10k Program/Erase cycles with 250 years of data retention.

CrossBar’s resistive RAM (ReRAM) technology can be used as a physical unclonable function (PUF) for generating cryptographic keys. The company said that using ReRAM instead of SRAM for PUFs provides a higher level of randomness, low bit error rate, resistance to invasive attacks, and the ability to handle a range of environmental variation.

Winbond’s OctalNAND Flash Memory is now interoperable with Synopsys’ DesignWare Synchronous Serial Interface (SSI) IP for a complete NAND flash solution with high-speed read bandwidth in densities up to 4Gbit targeted for automotive, mobile, and IoT SoCs.

Embedded, edge & IoT
Dolphin Design and CEA-List formed a joint R&D lab for embedded systems with the goal of identifying ideal tradeoffs in edge AI devices. CEA-List’s PNeuro hardware accelerator integrates AI into the computing platform developed in the joint lab and is combined with the processing platform developed by Dolphin Design. Dolphin Design also integrated several hardware IP developed by CEA-List into its Chameleon and Raptor product portfolio.

Infineon debuted a family of single-stage flyback controllers with constant voltage output optimized for cost-effective smart LED drivers. The ICL88xx family targets LED lighting applications, such as LED drivers and luminaires up to 125 W, smart lighting, and emergency luminaires, as well as adapters and chargers, flat TVs, all-in-one PCs and monitors up to 125 W.

HPC & quantum computing
The U.S. Department of Energy is putting $28 million toward funding five research projects aiming to make the most of supercomputing resources. The projects will focus on computational methods, algorithms and software to further chemical and materials research, specifically for simulating quantum phenomena and chemical reactions. “DOE’s national labs are home to some of the world’s fastest supercomputers, and with more advanced software programs we can fully harness the power of these supercomputers to make breakthrough discoveries and solve the world’s hardest to crack problems,” said U.S. Secretary of Energy Jennifer M. Granholm.

One of the projects, led by University of California Riverside and Lawrence Berkeley National Laboratory, aims to use high-performance exascale computing to control material systems with light. “Nearly all chemical, material, and biological processes occur out of equilibrium, and understanding how these systems can be controlled with light can enable numerous technologies such as solar materials, sensors, and light-harvesting nanomaterials,” said Bryan Wong, a professor of materials science and engineering at UC Riverside.

In separate funding, the DOE will spend $13 million on five projects to adapt scientific software to run on the coming generation of supercomputers.

The EU is also working to improve how software runs on supercomputers. The ADMIRE project, coordinated by the University Carlos III of Madrid (UC3M) and funded by the European High-Performance Computing Joint Undertaking (EuroHPC JU) and participating states, is developing a new adaptive storage system for high-performance computing. Parts of the effort include creating ad hoc storage systems, tools to adjust resources used by a program, optimization of processing pipelines, and the ability to process, compress, and analyze data during ongoing simulations. The project hopes to improve runtime of data-intensive applications in fields such as weather forecasting, molecular dynamics, turbulence modeling, cartography, brain research, and software cataloging.

Quantum computing startup Xanadu was awarded a DARPA grant to develop a unique general-purpose “circuit-cutting” compiler that can automatically break down a circuit into a multi-circuit hybrid model to leverage both classical and quantum computing. This would allow larger-scale computations without requiring more powerful quantum processors. “Using these tools, we plan to run quantum algorithms which would natively require 100+ qubits using quantum hardware and simulators containing only 10-30 qubits,” said Nathan Killoran, who heads up Xanadu’s Quantum Software & Algorithms team.

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