tag: Dolphin Design

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Nov, 2020 - Comments: 0

M&A Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec's sensors will be a key component to Synopsys' new Silicon Lifecycle Management (SLM) platform. "This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for de... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

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