Week In Review: Design, Low Power

RISC-V updates, VIP; open memory coherency bus; extending SoCs after manufacture.


RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, SoCs, developer boards, software and tools across computing from embedded to enterprise.” Early in the coming year, a number of new extensions, including Vector, Bit Manipulation, Scalar Cryptography, Packed SIMD, Secure PMP and Virtual Memory, will undergo public review. Security will be a focus, as well, with a new response process for potential security issues and upcoming cryptography extensions.

Imperas Software added to its RISC-V processor verification solutions with an enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, a new riscvOVPsimPlus free simulator, and a range of RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions. To support the SystemVerilog encapsulation of the reference model, the Imperas RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow. The free riscvOVPsimPlus RISC-V reference model and simulator has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options.

CHIPS Alliance and RISC-V International will work together to standardize an open unified memory coherency bus for data-centric applications using OmniXtend. “As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently.”

The OpenHW Verification Task Group collaborated with OneSpin Solutions to develop a verification plan that included formal methods to verify the family of CORE-V open-source RISC-V cores, including the OpenHW CV32E40P. These processors are intended to be integrated into high-volume, commercial chip projects with strict functional correctness, safety, trust, and security requirements.

Seagate jumped into the RISC-V ring, designing two processors based on the open ISA. One, optimized for high performance, targets real-time, critical HDD workloads and showed an increase the real-time processing power available in an initial use case. The second is optimized for area and power savings with a configurable microarchitecture and feature set for auxiliary, supporting, or background workloads and security-sensitive edge computational operations.

Tools & IP
Menta and Codasip are teaming up to allow joint customers to extend processors in SoCs after they have been manufactured. Using Codasip Studio, an existing processor design can be extended by adding custom instructions and additional microarchitectural features, which can be implemented on Menta’s co-extended eFPGA cores which are optimized for implementing processor functions.

Silexica launched a plugin for Xilinx’s Vitis Unified Software Platform to enable the addition of new pragmas and compiler optimizations when designing for FPGAs using high-level synthesis (HLS), including automatic loop transformations and automatic compiler transformations.

Aldec updated its Riviera-PRO verification tool to include the 2020.08 revision of the open-source VHDL verification methodology (OSVVM), which adds requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions. The tool also includes SystemVerilog and VHDL-2019 simulation enhancements.

Renesas expanded its IP licensing business with IP Utilities, a set of solutions aimed at simplifying the development of devices incorporating Renesas IP. It includes application packages for MCU development, early evaluation kits, IP core configuration tools, TCAM front end library, and EMC design consulting.

Think Silicon updated its NEMA|pico XS and NEMA|pico XL Multi-Core GPU IP-Series aimed at providing performance graphics rendering to the smallest and most power-conservative embedded display devices. The XS has CPU utilization of less than 5% and GPU power consumption under 1mW, is designed for devices where CPU, on-chip memory, battery and bandwidth are very limited. It is optimized to work with MCUs on a bare metal / RTOS. The XL is a 2.5D multicore GPU with multiple configurations and additional vector graphics and overlay extensions available.

Dolphin Design released a new version of its MAESTRO Power Controller RTL IP with dual operation mode, embedded sequencer, event-based architecture, and fast wake. Joining the IP is the PowerStudio compiler to speed up design and integration.

Intel debuted the second generation of its cryogenic control chips, which bring control functions for quantum computer operation to the cryogenic refrigerator that houses it. The Horse Ridge II SoC generates radio frequency pulses to manipulate the state of the qubit, known as qubit drive. It can read the current state of a qubit and provides capabilities for managing multiple qubits and reducing crosstalk.

OpenFive licensed Flex Logix’s EFLX eFPGA for use in a customer’s low power communications SoC targeted at data center and edge applications. OneFive cited the eFPGA’s density, performance, and the ability to do large arrays, as well as ease of integration.

Samsung Foundry is using Cadence’s Spectre X Simulator for its latest 5nm PCIe PHY IP for automotive, mobile, consumer and healthcare applications. Samsung cited a higher analog simulation capacity while increasing performance and maintaining accuracy.

AImotive adopted Synopsys’ VCS simulation and Verdi debug tools to help verify its aiWare hardware IP for Neural Network (NN) acceleration for automated driving applications, particularly targeting camera-centric solutions. AImotive cited improved coverage of its regression testing and overall team productivity.

Silicon Labs selected Imperas Software’s RISC-V reference model as part of its RISC-V processor verification work. The company cited the quality of the models and ease of use of the environment as well as experience with processor RTL DV flows.

The Centre for Development of Advanced Computing (C-DAC), an R&D organization of the Government of India, licensed Valtrix Systems’ STING verification platform for the verification of RISC-V based microprocessor design being developed for use in a number of strategic sectors.

XRby used Ansys’ optical design simulation software in its creation of luxury wristwatches to improve aesthetics, test watch assemblies, and evaluate materials and elements without physical prototype testing.

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