Week In Review: Design, Low Power

Keysight to acquire digital twin company; faster DDR5 DIMMs; high-frequency electromagnetics modeling for antennas; trapped ion quantum; FPGA-based emulation, prototyping; optical NoC; Samsung certifications.


Keysight Technologies said it intends to acquire ESI Group for €913 million (~$998.6 million). ESI Group provides virtual prototyping solutions for the automotive and aerospace end markets that can create real-time digital twins to simulate a product’s behavior during testing and real-life use.

MLCommons announced the latest results from two MLPerf benchmark suites. One aims to measure the performance of training machine learning models, while the other focuses on how quickly a trained neural network can process new data for extremely low-power devices in the smallest form factors.

How far can a RISC-V design be pushed and still be compliant? The answer isn’t always black-and-white, and defining exactly what compliance means remains a challenge.

Tools & products

AMD debuted its Versal Premium VP1902 adaptive SoC, a chiplet-based device for FPGA-based emulation and prototyping. The company says it has 18.5M logic cells for 2X capacity and 2X aggregate I/O bandwidth compared to the previous generation.

Renesas Electronics introduced its third generation DDR5 registered clock driver (RCD), as well as a first-generation client clock driver (CKD) for emerging DDR5 DRAM servers and client systems. The DDR5 RCD and DDR5 CKD ICs enable DIMMs with speeds of up to 6,400 and 7,200 megatransfers per second (MT/s), respectively.

Ansys expanded the upfront simulation capabilities in its Discovery platform to include high-frequency electromagnetics (EM) modeling for antennas. It automates the creation of EM regions based on desired frequency ranges and assigns conductive and dielectric material based on port definitions.

Lightelligence introduced an optical network-on-chip (oNoC) processor designed for domain-specific AI workloads. It uses vertically stacked packaging technologies to integrate a photonic chip and an electronic chip into a single package that implements a low-latency optical all-to-all broadcast network spanning 64 cores.

Infineon Technologies expanded its automotive microphone portfolio, adding the XENSIV MEMS microphone IM68A130A with a flat frequency response to frequencies below 10Hz for audio and active noise cancelation systems. Infineon also introduced two new barometric air pressure sensors targeted at automotive applications.

In a perfect world, a semiconductor device would be verified to operate according to its complete specification, and continue to operate correctly over the course of its useful life. The reality, however, is this is becoming much more difficult.

Bluespec uncorked a RISC-V embedded processor designed to enable developers to implement custom instructions and add accelerators to FPGAs and ASICs.

Dolphin Design debuted mixed-signal IP for voice and sound classification in battery-powered, always-on voice user interfaces, and always-on sound detection applications such as security cameras.

Flux updated its Copilot AI-powered PCB design assistant, adding automated component wiring through a chatbot-style interface.

Mojo Vision developed a 14K ppi red microdisplay for AR/XR with individual red micro-LEDs measuring 1.37um in diameter and set on a 1.87um pitch.


Samsung Foundry adopted Keysight Technologies’ IC-CAP Model Generator to accelerate the creation of circuit libraries, a key component of process design kits (PDKs) for Samsung’s advanced radio frequency (RF) semiconductor process technologies. The IC-CAP Model Generator software imports and organizes measured data and circuit netlists for various geometries and temperatures. In addition, the software automatically creates and simulates RF trend plots of key figures of merit based on user input.

OKI IDS adopted Siemens’ Catapult software for high-level synthesis (HLS) and high-level verification (HLV) in their design and verification services in the fields of information and telecommunications, medical electronics, and automated driving support.

Renesas adopted the Altium 365 cloud-based platform for development of all PCB design.

Quectel used Keysight’s network emulation solutions to verify support for RedCap and non-terrestrial networks by internet of things wireless modules.

Quadric joined Silicon Catalyst as an in-kind partner, making its general-purpose neural processor (GPNPU) IP available to startups in the semiconductor incubator program.

Industry CEOs discussed challenges in data sharing, and how to make sure chiplets will work as expected and that they are characterized consistently.

Samsung certifications

Ansys and Synopsys introduced a new reference flow for radio-frequency integrated circuit (RFIC) design developed with Samsung Foundry for its 14LPU process technology. The reference flow combines Ansys’ golden signoff electromagnetic analysis with Synopsys’ analog/RF and mixed-signal design and verification solution.

Ansys’ Redhawk-SC and Totem power integrity platforms were certified for Samsung’s latest 2nm silicon process technology. Additionally, the Redhawk-SC and Redhawk-SC Electrothermal power integrity and 3D-IC thermal integrity platform were certified for use with Samsung Foundry’s X-Cube technology for 3D packaging.

Cadence digital and custom/analog flows were certified for Samsung Foundry’s SF2 and SF3 process technologies. The two companies also worked together to create new process design kits (PDKs) for mobile, automotive, AI, and hyperscale IC design. Cadence also announced a certified backside implementation flow for Samsung’s SF2 process, support for Samsung’s 3D CODE standard in the Integrity 3D-IC platform, certification for the Virtuoso Studio design tools down to SF2, and a node-to-node design migration flow.

Siemens Digital Industries Software’s Calibre nmPlatform for IC sign-off was certified for Samsung Foundry’s latest 3nm process technologies, with enablement for the 2nm process underway. Additionally, Siemens’ Analog FastSPICE platform was certified for Samsung’s 18FDS, 14LPP, 14LPU, 11LPP, 8LPP, SF4, SF4P, SF3, and SF3P processes. The Aprisa place and route solution was certified for the SF5, and the companies also teamed up on a DFT flow and other solutions.

Synopsys’ 3D-IC Compiler reference flow and UCIe IP for die-to-die connectivity were certified for development of multi-die systems on Samsung Foundry’s 5nm, 4nm, and 3nm processes and I-Cube and X-Cube packaging technologies. Synopsys also announced optimized digital and custom design flows based on the Synopsys.ai EDA Suite for Samsung Foundry’s SF2 process.

Quantum computing

Infineon Technologies and eleQtron are partnering to develop trapped ion Quantum Processor Units (QPUs) for scalable quantum computers. eleQtron’s technology allows the control of qubits using radio frequency technology instead of lasers for low crosstalk between adjacent qubits. The companies will also investigate a novel, micro-structured 3D ion memory for a modular QPU architecture.

South Korea intends to spend more than 3 trillion won (~$2.3 billion) on quantum science and technology through 2035, according to Maeil Business News Korea. The effort will include building a superconductive quantum computer, along with advancing quantum sensors and communications. The government hopes to have a public-sector quantum foundry by 2031 and a private-sector quantum foundry by 2035.

Research notes

Researchers from the National Institute of Standards and Technology (NIST) proposed a way to reduce noise in quantum readouts. The device uses two superconducting qubits connected through a ‘toggle switch’ to a readout resonator. This toggle switch can be flipped into different states to adjust the strength of the connections between the qubits and the readout resonator, preventing circuit noise from creeping into the system through the readout resonator and reducing internal noise between the qubits.

Researchers from the University of Cambridge are developing resistive switching memory devices based on hafnium oxide that processes data in a similar way as the synapses in the human brain.

CEA launched a project to develop fully-depleted silicon-on-insulator (FD-SOI) chips that scale below 10nm, along with a new generation non-volatile onboard memory.

Upcoming events

  • DAC 2023: Design Automation Conference – July 9-13 (San Francisco, CA)
  • Rambus Design Summit – July 18-19 (Online)
  • 2023 Flash Memory Conference & Expo – August 8-10 (Santa Clara, CA)
  • DARPA: Electronics Resurgence Initiative (ERI) – August 22-24 (Seattle, WA)
  • Hot Chips 2023 – August 27-29 (Hybrid online & Stanford, CA)
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • Programming Processors In Heterogeneous Architectures
  • Power/Performance Costs Of Securing Systems
  • EDA’s Role Grows For Preventing And Identifying Failures
  • The Uncertainties Of RISC-V Compliance
  • Verification And Test Of Safety And Security
  • Better Choreography Required For Complex Chips
  • CEO Outlook: Chiplets, Data Management, And Reliability

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