Week In Review: Design, Low Power


Tools & IP Monozukuri unveiled its IC/Package co-design tool, GENIO. GENIO integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs.  It works seamlessly across all existing EDA flows and comprises floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization.... » read more

The Evolution Of High-Level Synthesis


High-level synthesis is getting yet another chance to shine, this time from new markets and new technology nodes. But it's still unclear how fully this technology will be used. Despite gains, it remains unlikely to replace the incumbent RTL design methodology for most of the chip, as originally expected. Seen as the foundational technology for the next generation of EDA companies around the ... » read more

Week In Review: Design, Low Power


Synopsys will acquire certain IP assets of INVECAS. The acquisition expands Synopsys' DesignWare Logic Library, General Purpose I/O, Embedded Memory, Interface and Analog IP portfolio. The acquisition will also add a team of experienced R&D engineers to focus on physical IP across a range of process technologies. INVECAS will retain its HDMI IP and ASIC Design Solutions businesses. The deal... » read more

Week In Review: Design, Low Power


Apple and Imagination inked a new multi-year license agreement under which Apple has access to a wider range of Imagination’s intellectual property in exchange for license fees. In 2017, Apple had announced it would be developing its own graphics chips and phasing out use of Imagination's IP. Imagination, which had recently restructured, saw its stock price fall by half in the wake of the new... » read more

RISC-V Markets, Security And Growth Prospects


Semiconductor Engineering sat down to discuss open instruction set hardware with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.  Part one of this discussion is ... » read more

RISC-V Challenges And Opportunities


Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation. (L-... » read more

Week In Review: Design, Low Power


Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

Week In Review: Design, Low Power


Intel disclosed a speculative execution side-channel attack method called L1 Terminal Fault (L1TF). Leslie Culbertson, Intel's executive vice president and general manager of Product Assurance and Security, writes: "This method affects select microprocessor products supporting Intel Software Guard Extensions (Intel SGX) and was first reported to us by researchers at KU Leuven University, Techni... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?


By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more