The basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and RISC-V processor cores from Bluespec.
Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including:
• Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard
• Static and formal property verification
• Equivalence checking
• Emulation and FPGA based verification
• Low power verification depending on the intended design application
• Verification using the Portable Stimulus Standard (PSS)
This white paper focuses on the first technique in this list. It explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and RISC-V processor cores from Bluespec.
Click here to read more.
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