A Unified Solution for End-to-End Low Power Verification

By Synopsys - 29 May, 2024 - Comments: 0

Low power designs are becoming increasingly prevalent in modern electronic systems, driven by the need for energy-efficient devices. Ensuring the correctness of these designs is paramount, as even minor errors can lead to catastrophic consequences. To achieve verification closure for low power designs, a combination of static verification, dynamic simulation-based verification, formal verificat... » read more

Maximizing Energy Efficiency For Automotive Chips

By William Ruby - 07 Mar, 2024 - Comments: 0

Silicon chips are central to today’s sophisticated advanced driver assistance systems, smart safety features, and immersive infotainment systems. Industry sources estimate that now there are over 1,000 integrated circuits (ICs), or chips, in an average ICE car, and twice as many in an average EV. Such a large amount of electronics translates into kilowatts of power being consumed – equiva... » read more

Understanding UVM Coverage For RISC-V Processor Designs

By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Run Realistic Software For Full Chip Power Signoff

By Godwin Maben - 09 Dec, 2021 - Comments: 0

In the real world, the demand for AI chips is driving the trend towards bigger, smarter, and faster SoC designs. Consequently, low-power design, analysis, verification, and power signoff challenges are not getting any easier as chip designs deploy increasingly smaller geometries that dissipate more and more power. Despite this dilemma, the quest for further power reductions continues apace. ... » read more

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

By Harry Foster - 08 Jul, 2021 - Comments: 0

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification trends in IC/ASIC language and library adoption, low power management, and verification effectiveness. We then take a deeper dive into two somewhat surprising phenomena revealed in the data: the ... » read more

An Integrated Approach To Power Domain And CDC Verification

By Kurt Takara - 11 Mar, 2021 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power... » read more

Customizing Low-Power Platforms Using UPF Dynamic Properties

By Progyna Khondkar - 12 Nov, 2020 - Comments: 0

Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

Probing UPF Dynamic Objects

By Mentor, a Siemens Business - 11 Nov, 2020 - Comments: 0

This paper presents a new low-power verification methodology that makes it possible to continuously monitor the dynamic properties of UPF objects and utilize the information to develop custom low-power verification environments. Based on UPF information model concepts, it allows querying of any dynamic properties of UPF objects through a Tcl API and passing object information on to appropriatel... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models

By Madhur Bhargava - 16 Jan, 2020 - Comments: 2

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

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