Writing Reusable UPF For RTL And Gate-Level Low Power Verification


By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts


Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, lev... » read more

What’s Working For Power Verification


Getting power verification right — or at least good enough — is the source of frustration for many design teams. Add to this the fact that there is no one right way to accomplish it just compounds the challenge. Fortunately, there are a number of options that are working to varying degrees, starting with static verification, according to Bernard Murphy, CTO of Atrenta. “Static verifica... » read more

Rethinking Low Power Verification: LP + CDC Verification


In my last posting, we discussed some of the barriers that companies face in seeking to meet their low power verification objectives, and how the complete and integrated technologies in Synopsys’ new Verification Compiler product can help. This time, I’d like to introduce a relevant example of how unified technology solutions can help address complex design interactions in low power verific... » read more

Is My iPhone Hurting The Earth?


Of course we all know that power is the number one consideration in SoC design today but despite the fact that it is so well accepted and felt acutely by design and verification teams, we are still missing the boat as far as the bigger picture. From the perspective of a wanna-be treehugger, I think we fall short in realizing the grand impact of all this focus on power savings. The very a... » read more

Rethinking Low Power Verification


The discussion of low power verification has been centered around design complexity growth multiplied (or exponentiated) by growth in adoption of low power design techniques. The main objectives seem clear – ensure that: The specification for the low power intent is valid The low power implementation matches the specification, and that its architecture, structure and behavior is valid ... » read more

Know What To Look For


With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

User Case Study


In prior articles I’ve written in general terms of about formally verifying the impact of adding low power control circuitry with Jasper’s Low Power Verification App. At the recent Jasper User’s Group meeting on Oct. 22, a real world case study of this app in action at STMicro’s R&D center in India was presented. Here are some highlights from this paper: DUT in question: an AR... » read more

Experts At The Table: Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Experts At The Table: Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate app... » read more

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