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Week In Review: Design, Low Power


Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Manufacturing Bits: Feb. 16


Hybrid bonding consortium for packaging A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications. The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONT... » read more

Manufacturing Bits: Dec. 29


Chiplet-based exascale computers At the recent IEEE International Electron Devices Meeting (IEDM), CEA-Leti presented a paper on a 3D chiplet technology that enables exascale-level computing systems. The United States and other nations are working on exascale supercomputers. Today’s supercomputers are measured in floating point operations per second. The world’s fastest supercomputers c... » read more