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Week In Review: Design, Low Power

112G XSR/USR PHY IP; cloud signoff; open source FPGA tools.

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Tools & IP
Rambus debuted 112G XSR/USR PHY IP on TSMC’s N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at various data rates.

Both Cadence and Synopsys worked with TSMC and Microsoft to improve performance of signoff tools running on Microsoft Azure.

Cadence’s Tempus Timing Signoff Solution provided scalability on 150 machines and 2X reduced timing signoff machine costs, while the Quantus Extraction Solution demonstrated near-linear scalability through 64 CPUs using multi-corner extraction.

Synopsys’ PrimeTime static timing analysis and StarRC parasitic extraction tools saw throughput gains by massively parallelizing the runs over hundreds of machines, and cost savings by running multiple scenarios on a single machine, when tested with a multi-million gate design using the TSMC N5 process and Azure’s Edsv4-series compute instances.

Arm updated its Mali Driver Development Kit (DDK) to support key requirements of automotive digital cockpit use-cases alongside Mali GPUs. The update provides new virtualization support capabilities for sharing of GPU resources between multiple graphically-rich applications running separate virtual machines. The virtualization features can be used across multiple operating systems and hypervisors and is designed to be invisible to applications.

QuickLogic uncorked its QORC (QuickLogic Open Reconfigurable Computing) initiative to support a fully open source suite of development tools for its MCUs, FPGA devices, and eFPGA technology. Developed by Antmicro in collaboration with QuickLogic and Google, initial open source development tools include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products will be added over the next few months.

Siemens expanded the Capital electrical system software, adding electrical/electronic systems development capabilities including support for software architectures, communication networks, and AUTOSAR compliant embedded software.

Silex Insight added two new variants of its FIPS 140-2 validated cryptographic coprocessor IP. Compact is designed for devices with strict power and area constraints, while Premium adds support for an isolated hardware key in addition to the standard features.

Deals & Certifications
Ambarella used Mentor’s Tessent Safety test ecosystem to meet in-system test requirements and achieve ISO 26262 ASIL goals for its CV22FS and CV2FS automotive camera SoC. Ambarella cited time-saving features that helped achieve design goals quickly and cost efficiently.

Several Synopsys Fusion Design Platform and Verification Continuum Platform products were qualified and made available through Samsung’s SAFE Cloud Design Platform. This allows customers to host their licenses in the SAFE Cloud Design Platform and use them along with Samsung Foundry’s process collateral in a secure environment.

Events
Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Or check out our latest Chip Basics video, Different Levels Of Interconnects, which explains how different layers at the chip level can affect the performance across a system.

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. Watch what’s new in this year’s content and focus. Keynotes for the event will cover a system look at semiconductor technology, the RISC-V revolution, wafer-scale deep learning accelerators, and looking ahead to 6G.



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