Week In Review: Design, Low Power

NPU plus DSP; Bunch of Wires for smaller projects; Codasip acquires for secure RISC-V; testing USB4; 433-qubit quantum processor.


Chip design

Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung’s 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of this work, we even managed to implement a data rate of 16 Gbit/s per lane — the highest rate specified by the BoW standard. We believe this provides an excellent basis for implementing forward-looking solutions for our customers and for a fruitful ongoing collaboration with Samsung,” said Andy Heinig, chiplet expert at Fraunhofer IIS/EAS.

Quadric announced a family of general-purpose neural processor (GPNPU) IP. The GPGPU IP blends the machine learning performance characteristics of a neural processing accelerator with the full C++ programmability of a modern digital signal processor (DSP). “Existing silicon solutions to the ML inference challenge have added accelerators as helper offload cores to existing DSPs or CPUs,” said Veerbhan Kheterpal, co-founder and CEO of Quadric. “The limitation of that approach is the clumsy way the programmer has to partition code across the different cores in the system and then tune the interaction between those cores to get desired performance goals. The new Chimera GPNPU family creates a unified, single-core architecture for both ML inference and related conventional C++ processing of images, video, radar, or other signals, eliminating multicore challenges.”

Keysight debuted a new suite of solutions for developing and validating new USB 80Gpbs implementations, including transmitter test software, receiver compliance test software, access to all Type-C signals via a live link, USB protocol trigger and decode, enhanced time-domain analysis, and IBIS-AMI model maker to facilitate the development of models for 80Gbps USB devices. “Synopsys USB controller, PHY and verification IP solutions leverage Keysight’s design and validation technologies to ensure robustness and compliance of the IP at maximum speeds,” said John Koeter, senior vice president of marketing and strategy for the Solutions Group at Synopsys.

Infineon launched a microcontroller (MCU) family for advanced industrial applications, including industrial drives, EV charging, two-wheel electric vehicles, and robotics. The XMC7000 series offers single and dual core options of 350-MHz 32-bit Arm Cortex-M7 and a 100-MHz 32-bit Arm Cortex-M0+, up to 8 MB of embedded flash and 1 MB of on-chip SRAM. The products operate from 2.7 to 5.5 V and achieve full specification from -40°C to 125°C. Infineon also announced a family of precise magnetic current sensing devices based on proprietary temperature and stress compensation for automotive applications.

Arm announced new partnerships that offer native integrations of its cloud-based development tools, including Arm Virtual Hardware. This includes the ability to use the Arm compiler and cross-compiler natively within GitHub Actions, as well as access Arm Virtual Hardware models of Corstone-based compute systems and Arm Cortex-M processors via self-hosted and GitHub-hosted runners. In addition, AutoML platforms Queexo and Nota AI are integrating Arm Virtual Hardware, which will be available as a development target on their platforms later this year. Arm also noted that MediaTek used its 2022 Total Compute Solutions portfolio of IP, including the Immortalis-G715 GPU and Cortex-X3 CPU, in its Dimensity 9200 SoC on TSMC 4nm.

Renesas expanded its partner ecosystem to include 106 new partners and 160 commercial-grade, performance-optimized building blocks for its RZ Family of 32-bit and 64-bit microprocessors. “Design complexity has expanded multi-fold, and project timelines are much tighter. Partner ecosystems are critically important to build whole solutions to address real-world engineering problems, enhance collaboration and drive success,” said Chip Rodgers, chief marketing officer of WorkSpan.

Without the benefits of scaling to help reduce power consumption, design teams must take responsibility themselves. It all starts with the architecture.

Nokia Bell Labs selected Keysight’s sub-Terahertz (THz) test bed to verify the performance of 5G advanced and 6G transceiver (TRX) modules. Modules to be tested use the radio frequency integrated circuit (RFIC) technology, including power amplifiers, transceivers, and antennas on a glass substrate, needed to support the data throughput and reliable backhaul transmission requirements of 5G advanced and 6G.

Purdue University and the Indian Institute of Technology Madras (IIT Madras) will launch a dual-degree master’s program in semiconductors as part of an agreement to cooperate in education and research in semiconductors and microelectronics. The partnership will also involve research collaboration in areas such as semiconductor supply chain management, chip design, packaging, system architecture, and advanced manufacturing methods.

Challenges mount, especially in 3D-ICs and chips developed at leading-edge nodes. Solving thermal coupling issues in complex chips is critical.


Samsung Electronics started mass production of a 1-terabit (Tb) triple-level cell (TLC) eighth-generation Vertical NAND (V-NAND). Based on the Toggle DDR 5.0 interface, it features an I/O speed of up to 2.4Gbps, a 1.2X boost over the previous generation. “As market demand for denser, greater-capacity storage pushes for higher V-NAND layer counts, Samsung has adopted its advanced 3D scaling technology to reduce surface area and height, while avoiding the cell-to-cell interference that normally occurs with scaling down,” said SungHoi Hur, executive vice president of Flash Product & Technology at Samsung Electronics.

Micron Technology started shipping qualification samples of its 1β (1-beta) DRAM technology. The node delivers around a 15% power efficiency improvement and more than a 35% bit density improvement with a 16Gb per die capacity compared to its 1α node.

Everspin Technologies announced commercial availability of its latest STT-MRAM family, which offers density up to 64Mb, octal interface with 400MB/s bandwidth, and compatibility with the xSPI standard. It targets applications where data persistence and integrity, low power, low latency, and security are important.

Weebit Nano said it received the first silicon wafers integrating its embedded Resistive Random-Access Memory (ReRAM or RRAM) module, manufactured in SkyWater Technology’s 130nm CMOS process.


Codasip acquired Cerberus Security Labs, a provider of IoT security IP. Cerberus’ embedded security IP will be integrated with Codasip’s products to embed secure functionality for RISC-V processor designs. Terms of the deal were not disclosed.

Secure-IC, a provider of cybersecurity solutions for embedded systems and connected objects, acquired Silex Insight’s security business, which provides security IP cores. “By handing over our security business to Secure-IC, we are assured that the customers are in the best hands to help them design devices with the highest security standards. At the same time customers will be able to design solutions that are scalable and can be updated in the field,” said Michel Van Maercke, CEO of Silex Insight. Terms of the deal were not disclosed.

Vishay Intertechnology, a manufacturer of discrete semiconductors and passive electronic components, acquired MaxPower Semiconductor, a fabless power semiconductor provider of silicon and SiC MOSFET products for automotive and industrial applications, for $50 million in cash and contingent payments of up to $57.5 million. “Importantly, this acquisition will enable Vishay to support customers’ advanced development of high voltage electrification applications thereby opening the door for us to provide them with our entire portfolio of products,” said Marc Zandman, executive chair of the board for Vishay.

Quantum computing

IBM unveiled its 433-qubit Osprey quantum processor. It more than triples the qubit count of last year’s generation, includes multi-level wiring to provide flexibility for signal routing and device layout, and adds in integrated filtering to reduce noise and improve stability. It also uses new high-density control signal delivery with flex wiring to provide a 70% increase in wire density and a 5x reduction in price-per-line. The company also detailed its IBM Quantum System Two, which combines multiple processors into a single system with communication links and is designed to be modular and flexible. It is expected to be available by the end of 2023 and include hybrid cloud middleware to integrate quantum and classical workflows. In software, it released a beta update to Qiskit Runtime, which includes allowing a user to trade speed for reduced error count with an option in the API.

The German Aerospace Center (DLR) awarded contracts totaling €208.5 million (~$209.3M) to several projects for the advancement of ion trap technology and building of prototype quantum computers. “By the end of the projects, we will have quantum computers based on ion trap technology, with at least 50 qubits. At the same time, we are building modular systems that can be scaled up to thousands of qubits,” said Robert Axmann, head of the DLR Quantum Computing Initiative. Specific projects involve building a 10-qubit demonstration model, prototype quantum computers with at least 50 functional qubits on a chip, and modular, scalable quantum computers that involve networking several chips to form a universal quantum computer architecture. Participants include eleQtron, NXP Semiconductors Germany, Parity Quantum Computing Germany, QUDORA Technologies and Universal Quantum Deutschland.

Upcoming events

Synopsys Memory Technology Symposium: Online, Nov. 29th, 2022 at 8:00 AM PST and Nov. 30th, 2022 at 8:00 AM GMT+8.

Supercomputing SC22: Nov. 13-18 in Dallas, Texas.

DAC 2023 deadlines: Abstracts for research papers are due Nov. 14. Workshop, tutorial, research session, and research panel proposals are due Nov. 21. Pavilion and engineering track proposals are due Jan. 17.

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