UCIe Goes Back To The Drawing Board


The integration of multiple dies within a single package increasingly is viewed as the next evolution for extending Moore’s Law, but it also presents myriad challenges — particularly in achieving a universally accepted standard integrating plug-and-play chiplets from different vendors. “In some respects, people are already doing this,” says Debendra Das Sharma, Intel senior fellow an... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing


Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

Auto Industry Relationships Re-Form, But Differently


The automotive industry is in the midst of rapid change on many fronts. OEMs are exploring new functions and features to add to their vehicles, including chiplets, electrification, autonomous features, as well as new vehicle architectures that will determine how vehicles are going to be designed from the foundation up. But all of this is dependent on the relationships between all of the ecosyst... » read more

Automotive Relationships Shifting With Chiplets


The automotive industry is in the midst of a tremendous and rapid change on many fronts. OEMs are exploring new functions and features to add to their vehicles, including chiplets, electrification, autonomous features, as well as new vehicle architectures that will determine how vehicles are going to be designed from the foundation up. All of this is dependent on the relationships between all o... » read more

Chiplets: More Standards Needed


Recent months have seen new advances in chiplet standardization. For example, consortia such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe) have made progress in developing standards for die-to-die (D2D) interfaces in a chiplet’s design. Far from being a new phenomenon in communication, these types of standards are established for all forms of wired and wireless com... » read more

Will AI Take My Job?


Everyone is talking about ChatGPT these days, and I am sure we will be comparing it with Google's new offering before long. I thought it was time that I gave it a quick spin, and since I am preparing to moderate a webinar about chiplets as I write this, I decided it was a good example of a fairly new field and would be a good test. I started by asking, "What are semiconductor chiplets, what ... » read more

Edge AI And Chiplets


In the near future, more edge artificial intelligence (AI) solutions will find their way into our lives. This will be especially true in the private sector for applications in the field of voice input and analysis of camera data, which will become well-established. These application areas require powerful AI hardware to be able to process the corresponding continuously accumulating data volumes... » read more

Is UCIe Really Universal?


Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

Week In Review: Design, Low Power


Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Raising IP Integration Up A Level


An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

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