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Week In Review: Design, Low Power


Synaptics will acquire DSP Group, a provider of voice and wireless chipset solutions for converged communications, at $22.00 per share in an all-cash transaction. The deal is worth $538 million. "We continue to invest in technologies that tilt our product mix toward IoT applications," said Michael Hurlston, President and CEO of Synaptics. "DSP Group's expertise in SmartVoice and ULE wireless so... » read more

Week In Review: Design, Low Power


Rambus is making a push for Compute Express Link (CXL) with two acquisitions and the launch of its CXL Memory Interconnect Initiative. The initiative aims to define and develop semiconductor solutions for advanced data center architectures, with initial research and development focusing on solutions to support key memory expansion and pooling use cases. CXL is an open interconnect specificat... » read more

Week In Review: Design, Low Power


Skyworks Solutions will acquire Silicon Labs' Infrastructure & Automotive (I&A) business for $2.75 billion cash. The transaction includes Silicon Labs' power/isolation, timing and broadcast products, intellectual property, and approximately 350 employees. Silicon Labs said it will focus on its IoT business, which includes integrated hardware and software wireless platforms for multiple ... » read more

Week In Review: Design, Low Power


Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices' December lawsuit alleging unauthorized use by Xilinx of eight ADI pate... » read more

Week In Review: Design, Low Power


Allegro DVT acquired Amphion Semiconductor, bringing together two developers of video codec IP. Allegro DVT said the merger will make it the first semiconductor IP company to offer commercially available hardware-based, real-time encoder and decoder solutions for the new AV1 video encoding format for SoC implementations, supporting 4K/UHD up to 8K. Based in Belfast, Northern Ireland, Amphion wa... » read more

Week In Review: Design, Low Power


Rambus completed its acquisition of Northwest Logic, a supplier of memory, PCIe and MIPI digital controllers. The Hillsboro, OR office of Northwest Logic will remain in place, along with the entire staff. SureCore launched a new low power design service. The company's offering includes concept-to-tape-out low power mixed-signal design expertise such as design and layout capabilities, technol... » read more

Target: 50% Reduction In Memory Power


Memory consumes about 50% or more of the area and about 50% of the power of an SoC, and those percentages are likely to increase. The problem is that static random access memory (SRAM) has not scaled in accordance with Moore's Law, and that will not change. In addition, with many devices not chasing the latest node and with power becoming an increasing concern, the industry must find ways to... » read more

Week In Review: Design, Low Power


Arm announced a new processor targeted at autonomous driving applications. The Cortex-A76AE is a superscalar, out-of-order processor that incorporates Split-Lock safety technology. Split-Lock allows CPU clusters in an a SoC to be configured either in ‘split mode’ for high performance, allowing two (or four) independent CPUs in the cluster to be used for diverse tasks and applications, or ... » read more

The Week In Review: Design


Tools Cadence unveiled an integrated memory design and verification tool, with environments for bitcell design, array and complier verification, and memory characterization. It utilizes existing simulation databases for multi-corner and Monte Carlo analysis, which the company says can lead to a 2X runtime improvement. Solido Design Automation uncorked PVTMC Verifier, which uses machine lear... » read more

Near-Threshold Computing


The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption. However, the situation changed at about 90nm in two ways. ... » read more

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