Cadence to buy Rambus SerDes, memory PHY biz; Ethernet for HPC; RTL restructuring issues; MCU market pricing; always-sensing edge AI; RTL implementation; power management in space.
Cadence will acquire Rambus’ SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP. “With this transaction, we will increase our focus on market-leading digital IP and chips and expand our roadmap of novel memory solutions to support the continued evolution of the data center and AI,” said Sean Fan, senior vice president and COO at Rambus. The transaction is expected to be immaterial to revenue and earnings this year for each company and is expected to close in Q3.
The Ultra Ethernet Consortium formed to build a complete Ethernet-based communication stack architecture for high-performance networking required by AI and HPC workloads. “This isn’t about overhauling Ethernet,” said J Metz, chair of the Ultra Ethernet Consortium. “It’s about tuning Ethernet to improve efficiency for workloads with specific performance requirements. We’re looking at every layer – from the physical all the way through the software layers – to find the best way to improve efficiency and performance at scale.” The consortium will work on minimizing communication stack changes while maintaining and promoting Ethernet interoperability. Organized as part of the Linux Foundation, founding members include AMD, Arista Networks, Broadcom, Cisco, Eviden, HPE, Intel, Meta, and Microsoft.
High-bandwidth memory (HBM) is becoming the memory of choice for hyperscalers, but there are still questions about its ultimate fate in the mainstream marketplace. While it’s well-established in data centers, with usage growing due to the demands of AI/ML, wider adoption is inhibited by drawbacks inherent in its basic design.
Yole Intelligence sees a shift in the microcontroller (MCU) market toward more advanced and higher-priced products. While the projected shipments of MCUs for 2023 indicate a decline of nearly 10% compared to 2022, the market research firm anticipates revenue to increase by 2% due to a surge in average selling prices (ASPs) of 12% year-over-year as the market holds onto the price increases resulting from manufacturing capacity scarcity caused by pandemic supply chain issues. Yole also expects semiconductor device revenue to retreat 7% from 2022 to $534 billion in 2023.
Check out Semiconductor Engineering’s coverage of DAC and SEMICON West, including top trends in chip design and equipment, U.S.-China relations, rising cybersecurity threats, and the interdependence of semiconductor devices and companies in manufacturing.
Expedera announced availability of its Origin E1 LittleNPU, a family of highly specialized AI inference edge processors for use in camera applications on smartphones, security cameras, home appliances, and other power-constrained devices.
Cadence unveiled a new tool for RTL design and implementation that provides insight into physical power, performance, area, and congestion effects. The Joules RTL Design Studio solution also provides logical, physical, and production implementation debugging information and leverages generative AI for RTL design exploration and big data analytics with actionable guidance on improving RTL. Socionext, MediaTek, Arm, and Alibaba noted using the tool.
Getting rid of heat is becoming much harder as transistor density increases. Just putting a large heatsink on the device can cause additional problems if proper analysis is not performed. Getting that right requires consideration for air flow and the mechanical design of the space in which it resides so that the impact on other devices is taken into account.
Synopsys uncorked a portfolio of interface IP for TSMC’s N3E process, including 112G Ethernet, LPDDR5X, DDR5, PCIe, USB/DisplayPort, and MIPI C/D-PHY IP.
Renesas Electronics debuted a complete space-ready reference design for the AMD Versal adaptive SoC XQRVC1902. The reference design integrates key radiation-hardened components for power management, including Pulse Width Modulation (PWM) controllers, GaN FET half-bridge drivers, point-of-load (POL) regulators, power and enable switches, and power sequencers. Additionally, Renesas’ automotive cybersecurity management system for MCU and SoC development was certified to ISO/SAE 21434:2021.
Keysight Technologies introduced a Layer 1-3 Ethernet performance test platform supporting data center interconnect speeds from 10GE to 800GE. It supports PAM4 and NRZ signaling along with all required forward error correction types and a full array of in-depth link tuning, stability, reliability, and performance measurement statistics. The company also announced support for the voluntary consumer IoT cybersecurity labeling program proposed by the U.S. government.
Rambus announced the first in a family of quantum-safe security IP products with its next-generation Root of Trust for data center and communications security. The new Root of Trust IP implements NIST-approved quantum-compute resistant cryptographic algorithms for key-encapsulation and digital signatures and supports Commercial National Security Algorithm Suite (CNSA) algorithms for software and firmware updates.
Infineon Technologies introduced two new ferroelectric RAM (F-RAM) memory devices in 1Mbit and 4Mbit densities. Targeting automotive event data recorders, the devices are AEC-Q100 Grade 1 qualified and support an extended temperature range with fast and reliable read/write performance at speeds up to 50 MHz in SPI mode and up to 108 MHz in Quad SPI (QSPI) mode, and an endurance of 10 trillion read/write cycles to support data logging at 10 microsecond intervals for over 20 years. Additionally, Infineon extended its 1200 V 62mm IGBT7 portfolio with a new 800 A maximum current class for the package family. Based on micro-pattern trench technology, the 62mm module family with the 1200 V TRENCHSTOP IGBT7 chip has lower static losses compared to modules with the IGBT4 chipset. The company also debuted a silicon carbide (SiC) MOSFET 650 V in TO leadless packaging, as well as a new generation of ultra-low ohmic high-side switches in a TO leadless package.
Automotive OEMs are starting to encounter some of the same issues chipmakers have been wrestling with at advanced nodes — massive compute performance, thermal and power issues, reliability over extended lifetimes, and a highly diverse and geographically distributed supply chain.
Samsung Electronics uncorked its GDDR7 DRAM. It features a total bandwidth of 1.5 TBps and a boosted speed per pin of up to 32Gbps using PAM3 signaling. The company also started mass production of a UFS 3.1 memory solution targeted at in-vehicle infotainment systems.
Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. This tech talk dives into grouping and ungrouping, re-parenting, and breaking connections logically, and explains why logical hierarchy must map to the physical hierarchy and where errors can creep into a design.
VSORA uncorked a single-chip architecture targeted at low-cost, low-power generative AI inferencing. The company says its chip provides 1.6 petaflops with 192 GB of on-chip memory and consumes less than 100W in a 45 x 45 mm package.
Xpeedic launched a high-speed digital signal integrity and power integrity (SI/PI) suite with support for advanced packaging and electromagnetic simulation.
Semidynamics announced a 64-bit RISC-V core with a 4-way pipeline, targeting applications that require large amount of data.
uPI Semiconductor used Ansys’ multi-physics simulation tools to speed up design of its product packaging solutions and improve thermal reliability of its power management chips for HPC applications.
Cadence, GlobalFoundries, Hoerzentrum Oldenburg, and Leibniz University Hannover teamed up to develop a binaural hearing aid SoC prototype that enables a wearer to pick up sounds from the full auditory scene without destroying the binaural cues. The programmable device enables development of hearing aids provide adaptive sound amplification customized to the wearer’s hearing needs.
TMY Technology deployed Ansys’ simulation software to improve the performance, efficiency, and quality of its mmWave antenna-in-package (AiP) designs for 5G and satellite communications.
Arm is partnering with Collabora to support development of an open-source Mali GPU driver for Linux.
SK Hynix used Siemens’ Polarion ALM application lifecycle management software in reaching ASPICE automotive semiconductor software quality certification.
Schneider Electric, Intel, and Applied Materials are teaming up on a program to encourage adoption of renewable energy throughout the semiconductor supply chain.
sureCore and Universal Quantum taped out a cryogenic IP demonstrator chip as part of an Innovate UK-funded project to develop a suite of foundation IP, including SRAM, standard cell, and IO cell libraries, that can be used to build interface chips capable of controlling and monitoring qubits at cryogenic temperatures.
Quantinuum simulated a chemical molecule by implementing a partially fault tolerant algorithm on a quantum processor using logical qubits.
RED Semiconductor and Crypto Quantique inked a deal to work on a microprocessor chip for implementing quantum-based security in edge devices.
HQS Quantum Simulations ran a quantum simulation algorithm on SEEQC’s full-stack quantum computing system.
Infleqtion and QinetiQ will work together to develop quantum algorithms to solve complex combinatorial optimization problems in logistics.
Alice & Bob said it achieved quantum control of its superconducting qubit with bit-flip times exceeding ten seconds and improved stabilization mechanisms.
Q-CTRL and Oxford Quantum Circuits plan to combine the former’s error suppression software with the latter’s hardware to improve algorithmic performance.
A team from the University of Science and Technology of China designed a low-jitter millimeter-wave all-digital phase-locked loop (CSS-ADPLL) chip using a charge-steering sampling technique. The CSS-ADPLL chip comprises a charge rudder discriminator (CSS-PD), a SAR-ADC, a digital filter, and a compact structure.
Researchers from Pennsylvania State University developed a thermoelectric cooler that could help control heat in future high-power electronics. The new thermoelectric device showed a 210% enhancement in cooling power density compared to a commercial device made of bismuth telluride, while potentially maintaining the ratio of useful cooling to energy required.
At the Israel Institute of Technology, Technion, researchers are working on ways to build novel semiconducting oxide thin films. The growth method involves picometer-level control over the distance between the material’s atoms, enabling creation of properties that could be useful in building future transistors.
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