Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)


A new technical paper, "Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning," was published by researchers at USC and University of Wisconsin-Madison. Abstract "Reasoning LLMs produce thousands of chain-of-thought tokens whose KV cache must reside in scarce GPU HBM. The dominant response -- permanently evicting low-importance tokens -- is catastrophic for reasoni... » read more

Research Bits: Apr. 14


Authentication for edge devices Researchers from the University of Hong Kong, Tsinghua University, and the Southern University of Science and Technology designed a privacy-preserving system for edge devices that combines physically unclonable functions and compute-in-memory. The Co-Located Authentication and Processing (CLAP) system integrates authentication and processing functions within ... » read more

Chip Industry Technical Paper Roundup: Dec 30


New technical papers recently added to Semiconductor Engineering’s library: [table id=509 /] Find more semiconductor research papers here. » read more

Research Bits: Dec. 22


Photonic memory Researchers from the University of Southern California Information Sciences Institute and the University of Wisconsin-Madison fabricated a regenerative photonic latch memory on GlobalFoundries’ commercial silicon photonics platform, a step towards building a complete photonic SRAM system. The memory cell can store data as light and regenerate the signal to keep it stable a... » read more

Reducing The Expertise Required For Software Developers To Participate In Chip Creation (USC)


A new technical paper titled "A Vertically Integrated Framework for Templatized Chip Design" was published by researchers at University of Southern California. Abstract "Developers who primarily engage with software often struggle to incorporate custom hardware into their applications, even though specialized silicon can provide substantial benefits to machine learning and AI, as well as ... » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)


A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

Research Bits: Nov. 4


Diffusive memristor for artificial neurons Researchers from the University of Southern California, University of Massachusetts, University of California Los Angeles, Syracuse University, and the Air Force Research Laboratory developed artificial neurons that replicate the complex electrochemical behavior of biological brain cells. “Our existing computing systems were never intended to pro... » read more

Research Bits: Sept. 23


Opto-electrical excitation of MTJs Researchers at the University of Greifswald, International Iberian Nanotechnology Laboratory, Max Planck Institute for the Science of Light, and Aarhus University advanced the use of magnetic tunnel junctions (MTJs) for neuromorphic computing. The team developed a hybrid opto-electrical excitation scheme that combines electrical currents with short laser p... » read more

For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency


Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI's power consumption. Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-so... » read more

Chip Industry Technical Paper Roundup: Nov. 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=381 /] More Reading Technical Paper Library » read more

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