Chip Industry Technical Paper Roundup: Mar. 11

Current-induced switching of ferromagnets; fault-resistant partitioning of CPUs; 2D tweezer array with 1000 atomic qubits; internal shielding for HW security; lowering simulation computational cost; tensor optical processor; attention sinks for streaming language models; variable-shaped beam mask writers and curvilinear full-chip inverse lithography.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Current-induced switching of a van der Waals ferromagnet at room temperature MIT
Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University
Make the impossible possible: use variable-shaped beam mask writers and curvilinear full-chip inverse lithography technology for 193i contacts/vias with mask-wafer co-optimization D2S and Micron
Supercharged two-dimensional tweezer array with more than 1000 atomic qubits TU Darmstadt
Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework Bar-Ilan University and Rafael Defense Systems
Accuracy of the explicit energy-conserving particle-in-cell method for under-resolved simulations of capacitively coupled plasma discharges Princeton University
Hypermultiplexed Integrated Tensor Optical Processor University of Southern California, MIT, City University of Hong Kong, and NTT Research
Efficient Streaming Language Models with Attention Sinks MIT, Meta AI, Carnegie Mellon University, and NVIDIA

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