Technical Paper Roundup: November 14

Nanowire FETs; laterally gated FeFETs for in-memory computing; LLMs for chip design; RowHammer mitigation; CMOS in-memory XOR/XNOR; electrical property quantification of memory devices; noise on quantum circuits; wireless NoC security review.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Fabrication and performance of highly stacked GeSi nanowire field effect transistors National Taiwan University
Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In22Se3 for stacked in-memory computing array Samsung Electronics and Sungkyunkwan University
ChipNeMo: Domain-Adapted LLMs for Chip Design NVIDIA
RAMPART: RowHammer Mitigation and Repair for Server Memory Systems Rambus
CMOS-based Single-Cycle In-Memory XOR/XNOR University of Tennessee, University of Virginia, and ORNL
In situ electrical property quantification of memory devices by modulated electron microscopy Hitachi High-Tech Corporation, KIOXIA Corporation, and Western Digital
The Discrete Noise Approximation in Quantum Circuits HQS Quantum Simulations
Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures Macquarie University

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