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Technical Paper Roundup: Sept. 12


New technical papers added to Semiconductor Engineering’s library this week. [table id=51 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Scaling Down To 2nm: Using Microwaves For Efficient & Stable Doping


A new technical paper titled "Efficient and stable activation by microwave annealing of nanosheet silicon doped with phosphorus above its solubility limit" was just published by researchers at National Taiwan University, Cornell University, TSMC, University of Valladolid, DSG Technologies, National Central University and National Yang Ming Chiao Tung University. A modified microwave was used... » read more

Security Research: Technical Paper Round-Up


A number of hardware security-related technical papers were presented at recent conferences, including the August 2022 USENIX Security Symposium and IEEE’s International Symposium on Hardware Oriented Security and Trust (HOST). Topics include side-channel attacks and defenses (including on-chip mesh interconnect attacks), heterogeneous attacks on cache hierarchies, rowhammer attacks and mitig... » read more

Assessing & Simulating Semiconductor Side-Channel or Unintended Data Leakage Vulnerabilities


This research paper titled "Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification" from researchers at Ansys, National Taiwan University and Kobe University won the best paper award at IEEE's International Symposium on Hardware Oriented Security and Trust (HOST). The paper presents a new tool "to assess unintended data leakage vulnerabilities... » read more

Technical Paper Round-up: May 17


New technical papers added to Semiconductor Engineering’s library this week. [table id=27 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a go... » read more

SOT-MRAM-based CIM architecture for a CNN model


New research paper "In-Memory Computing Architecture for a Convolutional Neural Network Based on Spin Orbit Torque MRAM", from National Taiwan University, Feng Chia University, Chung Yuan Christian University. Abstract "Recently, numerous studies have investigated computing in-memory (CIM) architectures for neural networks to overcome memory bottlenecks. Because of its low delay, high energ... » read more

Solution Processable Pentafluorophenyl EndCapped Dithienothiophene Organic Semiconductors for Hole Transporting Organic Field Effect Transistors


Abstract: "Two solution‐processable organic semiconductors, DFPT‐DTTR (1) and DFPbT‐DTTR (2), composed of pentafluorophenyl (FP) end‐capped 3,5‐dialkyl dithienothiophene (DTTR) core with thiophene (T) or bithiophene (bT) as π‐bridged spacers are developed and investigated for their optical, electrochemical, microstructural, and electrical properties. With more conjugated bithiophe... » read more

Data-driven Scheduling for High-mix and Low-volume Production in Semiconductor Assembly and Testing


Abstract: The objective of this research is to improve scheduling decisions in high-mix low-volume (HMLV) production environments. Unique characteristics of HMLV semiconductor assembly and testing operations include: (1) Diversified Product Lines: To respond to global competition and different customer needs, manufacturers are providing diversified products to different consumers; (2) Unrelate... » read more

Manufacturing Bits: July 14


Complementary FETs At the recent 2020 Symposia on VLSI Technology and Circuits, Imec presented a paper on a 3D complementary field-effect transistor (CFET) made on 300mm wafers. As a demonstration vehicle, Imec showed a CFET based on a 14nm process. Ideally, though, CFETs are next-generation transistors that are targeted for the 1nm node in the future. On the transistor front, chipmaker... » read more

Efficient Spin-Orbit Torque Switching with Non-Epitaxial Chalcogenide Heterostructures


Abstract: "The spin–orbit torques (SOTs) generated from topological insulators (TIs) have gained increasing attention in recent years. These TIs, which are typically formed by epitaxially grown chalcogenides, possess extremely high SOT efficiencies and have great potential to be employed in next-generation spintronics devices. However, epitaxy of these chalcogenides is required to ensure the... » read more

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