On-package memory with UCle; LLM circuit simulator; AMS circuit AI agent; 3DIC thermo-mechanical behavior; AI analog building block sizing; purity in the IC industry; 3D chip-to-chip photonic interconnects; process-induced warpage; EUV photoresists imaging; CryptoSRAM; DRAM address-mapping reverse engineering.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach | AMD, Intel Corporation |
| The Impact of Process Variations on the Thermo-Mechanical Behavior of 3D Integrated Circuits | National Taiwan University, Lamar University |
| From Systematic to Intelligent: Assessing AI-Empowered Optimization Techniques for Analog Building Block Sizing | U. of Glasgow, Mediatek, U. of Edinburgh, Magics, U. of Sevilla, Georgia Tech |
| Process-Induced Warpage Behavior in Backside Power Delivery Network Fabrication | Korea University, Georgia Tech |
| Purer than pure: how purity reshapes the upstream materiality of the semiconductor industry | RMIT, Université catholique de Louvain, U. of Edinburgh |
| Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects | TH Wildau, TH Mittelhessen, TU Ilmenau, BTU, Fraunhofer IPMS |
| Initial stage of nanoscale imaging in positive-tone extreme UV photoresists: the influence of polymer sequence | Berkeley Lab, Columbia Hill Technical Consulting |
| CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing | UC Riverside |
| Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering | Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA |
Find more semiconductor research papers here.
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