Chip Industry Technical Paper Roundup: Jun. 2


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Physical Foundation Models: Fixed HW implementations of large-scale neural networks 🔗 Yale University, Cornell University, Boston University, NTT Research Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Princip... » read more

Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

Electrical Model of the Bitflip in SRAM Under Laser Illumination Simulating Laser Fault Injection


A new technical paper, "Electrical modelisation of a bitflip in SRAM cell memory induced by laser fault injection," was published by researchers at Univ Rennes, CNRS, IETR. Abstract "An electrical model of the bitflip in SRAM under laser illumination simulating laser fault injection is proposed. This model is based on a bipolar phototransistor responsible of the amplified induced photocur... » read more

Chip Industry Technical Paper Roundup: Oct. 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=482 /] Find more semiconductor research papers here. » read more

Algorithms For Black-Box, Physical-to-DRAM Address-Mapping Recovery (Georgia Tech, CNRS, Et Al.)


A new technical paper titled "Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering" was published by researchers at Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA. Abstract "Modern Systems-on-Chip (SoCs) employ undocumented linear address-scrambling functions to obfuscate DRAM addressing, which complicates DRAM-aware performance optimizations and hind... » read more

Research Bits: Sept. 30


Hybrid memory for edge training and inference Researchers from CEA-Leti, Université Grenoble Alpes, CEA-List, the French National Centre for Scientific Research (CNRS), the University of Bordeaux, Bordeaux INP, IMS France, Université Paris-Saclay, and the Center for Nanosciences and Nanotechnologies developed a hybrid memory system that combines the traits of ferroelectric capacitors (FeCAP)... » read more

Chip Industry Technical Paper Roundup: August 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=463 /] Find more semiconductor research papers here. » read more

Optical Next-Gen Reservoir Computing Framework (Sorbonne, CNRS, Tsinghua U. et al)


A new technical paper titled "Optical next generation reservoir computing" was published by researchers at Sorbonne Université, CNRS, Tsinghua University, University of Hong Kong, and University of Tokyo. Excerpt "Artificial neural networks with internal dynamics exhibit remarkable capability in processing information. Reservoir computing (RC) is a canonical example that features rich comp... » read more

Chip Industry Technical Paper Roundup: May 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=427 /] Find more semiconductor research papers here.   » read more

Hardware Trojan Attack For SNNs (Sorbonne Université, CNRS)


A new technical paper titled "Input-Triggered Hardware Trojan Attack on Spiking Neural Networks" was published by researchers at Sorbonne Universite, CNRS and Queen’s University Belfast. Abstract "Neuromorphic computing based on spiking neural networks (SNNs) is emerging as a promising alternative to traditional artificial neural networks (ANNs), offering unique advantages in terms of low... » read more

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