Fixed HW implementations of neural networks; LLM inference scaling; silent data corruption detection; NAND flash tunneling; HW-SW co-design benchmarks for SoCs; chiplet side-channel attacks; GPU power management.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Physical Foundation Models: Fixed HW implementations of large-scale neural networks 🔗 | Yale University, Cornell University, Boston University, NTT Research |
| Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles 🔗 | Micron Technology, Argonne National Laboratory |
| ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions 🔗 | Stanford University, Google |
| Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory 🔗 | University of Seoul, Samsung Electronics |
| HSCO-Bench: An Agent-Driven End-to-End HW-SW Co-design Benchmark for Systems-on-Chip 🔗 | Columbia University, IBM Research |
| Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems 🔗 | Grenoble INP – UGA, CNRS, TIMA |
| CompPow: A Case for Component-level GPU Power Management 🔗 | AMD |
Find more semiconductor research papers here.
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