Chip Industry Technical Paper Roundup: Jun. 2


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Physical Foundation Models: Fixed HW implementations of large-scale neural networks 🔗 Yale University, Cornell University, Boston University, NTT Research Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Princip... » read more

Building Fixed HW Implementations of Neural Networks (Yale, Cornell et al.)


Researchers from Yale University, Cornell University, Boston University, and NTT Research have published “Physical Foundation Models: Fixed hardware implementations of large-scale neural networks”. Abstract "Foundation models are deep neural networks (such as GPT-5, Gemini~3, and Opus~4) trained on large datasets that can perform diverse downstream tasks -- text and code generation, q... » read more

Chip Industry Week In Review


Deals, Funding Intel will join Elon Musk’s Terafab chip manufacturing project alongside Tesla, SpaceX, and xAI. Intel described its role as helping refactor silicon fab technology for a project targeting production of 1 TW/year of compute for AI and robotics applications. Intel and Google are expanding a multi-year collaboration on AI and cloud infrastructure, with Intel Xeon processo... » read more

Research Bits: Mar. 3


Computational electron microscopy Researchers from Cornell University, TSMC, and ASM used electron ptychography for atomic-scale defect inspection of transistors. The computational imaging method uses an extremely precise electron microscope pixel array detector (EMPAD) to collect detailed scattering patterns of electrons after they pass through transistors and compare how the patterns chan... » read more

Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

Chip Industry Week In Review


Big Deals and Fundings Rapidus secured US$1.7B in a new funding round from the Japanese government and the private sector to ramp 2nm production by next year. Open AI announced a $110B in new funding, with $30B from Nvidia, $30B from Softbank and $50B from Amazon. In a $100B multi-year deal, Meta will power its AI infrastructure with up to 6GW of AMD's GPUs. SambaNova and Intel ar... » read more

3D Atomic-Scale Metrology of Strain Relaxation And Roughness in GAAFETs Via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper, "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography," was published by researchers at Cornell University, ASM and TSMC. Abstract "Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale me... » read more

Chip Industry Technical Paper Roundup: Feb. 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=519 /] Find more semiconductor research papers here. » read more

Semiconductor Supply Chain Security Using Side-Channel Power Measurements and Generative Adversarial Networks (Cornell)


A new technical paper titled "Out-of-Band Power Side-Channel Detection for Semiconductor Supply Chain Integrity at Scale" was published by researchers at Cornell University. Abstract "Out-of-band screening of microcontrollers is a major gap in semiconductor supply chain security. High-assurance techniques such as X-ray and destructive reverse engineering are accurate but slow and expensiv... » read more

Chip Industry Week in Review


SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

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