Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Research Bits: April 8


Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

Research Bits: Feb. 19


DNA assembly of 3D nanomaterials Scientists from Brookhaven National Laboratory, Columbia University, and Stony Brook University developed a method that uses DNA to instruct molecules to organize themselves into targeted 3D patterns and produce a wide variety of designed metallic and semiconductor 3D nanostructures. “We have been using DNA to program nanoscale materials for more than a de... » read more

Chip Industry Technical Paper Roundup: Feb. 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=199 /] More ReadingTechnical Paper Library home » read more

New Metasurface Architecture To Deliver Ultrafast Information Processing And Versatile Terahertz Sources


A technical paper titled “Light-driven nanoscale vectorial currents” was published by researchers at Los Alamos National Laboratory, Menlo Systems, University of California Davis, Columbia University, Sandia National Laboratories, and Intellectual Ventures. Abstract: "Controlled charge flows are fundamental to many areas of science and technology, serving as carriers of energy and informa... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Hacking DNA To Make 3D Nanostructures


A technical paper titled “Three-dimensional nanoscale metal, metal oxide, and semiconductor frameworks through DNA-programmable assembly and templating” was published by researchers at Brookhaven National Laboratory, Columbia University, and Stony Brook University. Abstract: "Controlling the three-dimensional (3D) nanoarchitecture of inorganic materials is imperative for enabling their no... » read more

Research Bits: November 6


Fast superatomic semiconductor Researchers from Columbia University created a fast and efficient superatomic semiconductor material based on rhenium called Re6Se8Cl2. Rather than scattering when they come into contact with phonons, excitons in Re6Se8Cl2 bind with phonons to create new quasiparticles called acoustic exciton-polarons. Although polarons are found in many materials, those in Re6Se... » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

Measurement-Induced Quantum Information Phases On Up To 70 Superconducting Qubits (Google/Stanford)


A technical paper titled “Measurement-induced entanglement and teleportation on a noisy quantum processor” was published by researchers at Google Quantum AI, Google Research, Stanford University, University of Texas at Austin, Cornell University, University of Massachusetts, University of Connecticut, Auburn University, University of Technology Sydney, University of California, and Columbia... » read more

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