Chip Industry’s Technical Paper Roundup: Jan 3


New technical papers added to Semiconductor Engineering’s library this week. [table id=72 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Graphene-Based Electronics (Georgia Tech)


A technical paper titled "An epitaxial graphene platform for zero-energy edge state nanoelectronics" was published by researchers at Georgia Tech, Tianjin University, CNRS, Synchrotron SOLEIL, National High Magnetic Field Laboratory and others. “Graphene’s power lies in its flat, two-dimensional structure that is held together by the strongest chemical bonds known,” said Walter de Heer... » read more

Week In Review: Design, Low Power


Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Chip Industry’s Technical Paper Roundup: Nov. 29


New technical papers added to Semiconductor Engineering’s library this week. [table id=66 /]   Related Reading: Chip Industry’s Technical Paper Roundup: Nov. 21 New papers: lithography modeling; solving Rowhammer; energy-efficient batch normalization HW; 3-to-1 reconfigurable analog signal modulation circuit; lateral double magnetic tunnel junction; reduce branch mispredic... » read more

3D Structuring Inside GaAs by Ultrafast Laser Inscription


A new technical paper titled "Burst mode enabled ultrafast laser inscription inside gallium arsenide" was published by researchers at LP3 Laboratory in France, a joint research unit of Aix-Marseille University (AMU) and CNRS. "We investigate the possibility of using THzrepetition-rate burst mode for ULI inside GaAs, a material that cannot be internally processed with single femtosecond pulse... » read more

Chip Industry’s Technical Paper Roundup: Nov. 1


New technical papers added to Semiconductor Engineering’s library this week. [table id=61 /] » read more

Chip Industry’s Technical Paper Roundup: Oct 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=57 /] » read more

Accelerating Off-Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path


A new technical paper titled "Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction" was published by researchers at ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS.  The work received a best paper award at MICRO 2022. Abstract "Long-latency load requests continue to limit the performance of high-performance ... » read more

Chip Industry’s Technical Paper Roundup: Oct. 4


New technical papers added to Semiconductor Engineering’s library this week. [table id=55 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Spin–Orbit Qubit With A Single Hole Electrostatically Confined In A Natural Silicon Metal-Oxide-Semiconductor Device


A new technical paper titled "A single hole spin with enhanced coherence in natural silicon" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Semiconductor spin qubits based on spin–orbit states are responsive to electric field excitations, allowing for practical, fast and potentially scalable qubit control. Spin electric susceptibility, however,... » read more

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