Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)


A new technical paper titled “Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels” was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill.


“In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and multi-wire (MW) reconfigurable field-effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on- and off-currents as well as threshold voltages for n- and p-type operation exhibit a high degree of symmetry. Most notably also a low device-to-device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired-AND gate obtained from a multi-gate RFET. Additionally, up-scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self-learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.”

Find the technical paper here. Published December 2023.

L. Wind, R. Behrle, M. I. den Hertog, C. G. E. Murphey, J. F. Cahoon, M. Sistani, W. M. Weber, Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels. Adv. Electron. Mater. 2023, 2300483. https://doi.org/10.1002/aelm.202300483.

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