Chip Industry Week In Review


Deals IBM and Arm are collaborating on a new dual‑architecture hardware aimed at enterprise AI and data-intensive workloads, using virtualization to boost reliability, security, scalability, and software compatibility. The goal, according to an IBM spokesperson, is to deliver side-by-side deployments of S390x-Linux and Arm-Linux virtual machines in a single kernel-based hypervisor. Nv... » read more

Chip Industry Week In Review


Disruptions caused by the Iran conflict have taken about one third of the global helium supply off the market, an essential gas for semiconductor manufacturing, reports the World Economic Forum. Other potential impacts for the chip industry include bromine and other chemical shortages, logistical disruptions, and higher energy prices incurred by fabs in Asia. Top Deals IBM and Lam R... » read more

Research Bits: Jan. 27


Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

Chip Industry Technical Paper Roundup: Jan. 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=515 /] Find more semiconductor research papers here. » read more

Chip Industry Technical Paper Roundup: Jan 12


New technical papers recently added to Semiconductor Engineering’s library: [table id=513 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

SiGeSn SBFETs at Cryogenic Temperatures (Tu Wien et al)


A new technical paper titled "A Cryogenic Ultra-Thin Body SiGeSn Transistor" was published by researchers at TU Wien, Johannes Kepler University, Universidad de Granada, and Max Planck Institute for Sustainable Materials. Abstract "Transistors capable of operating at cryogenic temperatures are key components for the fast and energy-efficient control and readout of qubits. However, the ultra... » read more

Chip Industry Technical Paper Roundup: Dec. 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=497 /] Find more semiconductor research papers here. » read more

On-Current Performance of Ultra-Scaled NSFETs With Source/Drain Underlap Doping (Global TCAD Solutions, TU Wien)


A new technical paper titled "On-Current Degradation in Ultra-Scaled Nanosheet FETs with S/D Underlap Doping" was published by researchers at Global TCAD Solutions GmbH and TU Wien. Abstract: "Aggressive gate pitch scaling makes it increasingly challenging to control the doping gradient at the source/drain (S/D) extensions. To address this, S/D underlap doping has been proposed as a solutio... » read more

Chip Industry Technical Paper Roundup: Nov. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=490 /] Find more semiconductor research papers here. » read more

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