Accelerating large-context LLM attention; leakage reduction in RTL code generation; GPU edge inference performance; etching resistance in EUV nanopatterns; vdW gap bottleneck; memtransistors for decentralized edge; DL simulation on chiplets; JJFETs cryogenic, quantum applications.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| The van der Waals Gap: a Hidden Showstopper in Semiconductor Device Scaling | TU Wien |
| Enhanced Edge Etching Resistance and EUV Lithographic Performance of a Tin-Oxide Photoresist via a Blend Strategy | National Tsing Hua University |
| LongSight: Compute-Enabled Memory to Accelerate Large-Context LLMs via Sparse Attention | Cornell University |
| CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage | University of Central Florida |
| EdgeReasoning: Characterizing Reasoning LLM Deployment on Edge GPUs | NVIDIA |
| Large-scale crossbar arrays based on three-terminal MoS2 memtransistors | Penn State University, Naval Information Warfare Center Pacific |
| CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems | University of Wisconsin–Madison, Washington State University |
| Silicon-based Josephson junction field-effect transistors enabling cryogenic logic and quantum technologies | University of Glasgow |
Find more semiconductor research papers here.
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