Chip Industry Week In Review


Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Chip Industry Week In Review


TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

Chip Industry Technical Paper Roundup: Nov. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=490 /] Find more semiconductor research papers here. » read more

Balancing Leakage Reduction with Correctness Preservation in RTL Code Generation (Univ. of Central Florida)


A new technical paper titled "CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage" was published by researchers at University of Central Florida. Abstract "Large Language Models (LLMs) have achieved remarkable success in generative tasks, including register-transfer level (RTL) hardware synthesis. However, their tendency to memorize training data poses critic... » read more

Chip Industry Week in Review


SK hynix is ramping HBM manufacturing capacity to meet explosive demand for AI data centers. The company will launch 16-stack HBM4 next year, and up to 12-stack HBM4E. HBM5 and HBM5E will be introduced between 2029 and 2031, reports Business Korea. China will not have access to NVIDIA’s most advanced chips, President Trump told 60 Minutes. The Dutch economy minister said Nexperia's chip... » read more

Chip Industry Week in Review


The Open Compute Project (OCP) Summit kicked off this week in San Jose, dominated by open standards, massive scaling of AI infrastructure, chiplet architectures, and energy-efficiency. Among the highlights: An initiative to standardize data center infrastructure and advance Ethernet for AI. New contributions to OCP's Open Chiplet Economy ecosystem, including Arm's new Foundation Chiplet... » read more

Chip Industry Technical Paper Roundup: Oct. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=480 /] Find more semiconductor research papers here » read more

Distributed Authentication Framework Leveraging Multi-Party Computation In A Scalable Tree-Based Architecture (Univ. of Central Florida, Louisiana State)


A new technical paper titled "AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems" was published by researchers at University of Central Florida and Louisiana State University. Abstract "The rapid adoption of chiplet-based heterogeneous integration is reshaping semiconductor design by enabling modular, scalable, and faster time-to-market s... » read more

Chip Industry Technical Paper Roundup: Sept 23


New technical papers recently added to Semiconductor Engineering’s library: [table id=478 /] Find more semiconductor research papers here. » read more

Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)


A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

← Older posts