Chip Industry’s Technical Paper Roundup: Jan 3
Area-efficient RISC-V decoupled vector coprocessor for HPC; rowhammer mitigation; HW accelerator; epitaxial graphene platform; power electronics; MTJ for stochastic computing; clock gating; paper-thin solar cells added to any surface; data transmission using inverse-designed silicon photonics.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper |
Research Organizations |
| Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications |
Barcelona Supercomputing Center, Spain |
| REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations |
Computer Security Group (COMSEC), ETH Zurich and Zentel Japan |
| CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data |
MIT, IBM TJ Watson, SRI International, and University of Michigan |
| An epitaxial graphene platform for zero-energy edge state nanoelectronics |
Georgia Tech, Tianjin University, CNRS, Synchrotron SOLEIL, National High Magnetic Field Laboratory and others |
| Perspectives on MOVPE-grown (100) β-Ga2O3 thin films and its Al-alloy for power electronics application |
Leibniz-Institut für Kristallzüchtung (IKZ), Germany |
| Review of Magnetic Tunnel Junctions for Stochastic Computing |
University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others |
| A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers |
Università degli Studi di Catania, Italy |
| Printed Organic Photovoltaic Modules on Transferable Ultra-thin Substrates as Additive Power Sources |
MIT |
| Multi-dimensional data transmission using inverse-designed silicon photonics and microcombs |
Stanford, Harvard, University of Central Florida, NIST, and others |
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Chip Industry’s Technical Paper Roundup: Dec. 20
Heterogeneous ultra-low-power Linux capable RISC-V SoC; fuzzing HW; layout automation; parallelization of 5G PUSCH on RISC-V; repurposed Josephson Junctions; chirality logic gates; SRAM security risk; fast-lock digital clock generator for chiplets; suppressing vibrations on graphene devices; RL for design space exploration.
Linda Christensen
(all posts)
Linda Christensen is vice president of operations and a contributing writer at Semiconductor Engineering.
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