Chip Industry’s Technical Paper Roundup: Dec. 20

Heterogeneous ultra-low-power Linux capable RISC-V SoC; fuzzing HW; layout automation; parallelization of 5G PUSCH on RISC-V; repurposed Josephson Junctions; chirality logic gates; SRAM security risk; fast-lock digital clock generator for chiplets; suppressing vibrations on graphene devices; RL for design space exploration.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC University of Bologna, University of Modena and Reggio Emilia, and ETH Zurich
Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor ETH Zurich
Fuzzing Hardware Like Software University of Michigan, Google and Virginia Tech
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies UT Austin and NVIDIA
Multi-Agent Reinforcement Learning for Microprocessor Design Space Exploration Harvard University and Google research groups
Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions UC Santa Barbara
Chirality logic gates Aalto University (Finland), National Center for Nanoscience and Technology (Beijing), and University of Cambridge
Beware of Discarding Used SRAMs: Information is Stored Permanently Auburn University
Graphene Devices: Suppressing Vibrations By Adding Vibrations ARC Centre of Excellence in Future Low-Energy Electronics Technologies (FLEET), Monash University and University of Melbourne
A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems Hongik University

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More Reading
Technical Paper Library home
Chip Industry’s Technical Paper Roundup: Dec. 13
2D materials special issue; measuring direct bonding at wafer scale; information flow for HW; hafnium oxide-based FeFETs for in-memory; fully rubbery Schottky diodes and ICs; layered HW security for cloud and edge; neural architecture and HW accelerator co-design framework.

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