Chip Industry Technical Paper Roundup: Feb. 13


New technical papers added to Semiconductor Engineering’s library this week. [table id=197 /] More ReadingTechnical Paper Library home » read more

Modeling And Analyzing Open-Source SoCs For Low-Power Cyber-Physical Systems


A technical paper titled “TOP: Towards Open & Predictable Heterogeneous SoCs” was published by researchers at University of Bologna, ETH Zurich, and University of California San Diego. Abstract: "Ensuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An... » read more

Technical Paper Roundup: November 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=169 /] More Reading Technical Paper Library home » read more

A Fast And Unified Toolchain For Rapid Design Space Exploration Of Chiplet Architectures


A technical paper titled “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet ... » read more

Fast Interrupt Extension For MCU RISC-V


A technical paper titled “CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handl... » read more

Chip Industry’s Technical Paper Roundup: Sept 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=141 /] More Reading Technical Paper Library home » read more

A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters


A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

Week In Review: Design, Low Power


DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

Chip Industry’s Technical Paper Roundup: June 20


New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators


A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

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