Chip Industry’s Technical Paper Roundup: Sept 19

Formally verifying data-oblivious behavior in HW; extensible DRAM simulator; instruction cache for ULP processor clusters; evaluating RISC-V for HPC; sequestered encryption architecture; copper-iodide-based artificial synaptic device; perovskite-derivative nickelate’s electrical conduction; practical hardware for evolvable robots.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
A Scalable Formal Verification Methodology for Data-Oblivious Hardware RPTU Kaiserslautern-Landau and Stanford University
Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator ETH Zurich
Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters University of Bologna, ETH Zurich, and GreenWaves Technologies
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU University of Edinburgh
Security Verification of Low-Trust Architectures Princeton University, University of Michigan, and Lafayette College
Charge-Mediated Copper-Iodide-Based Artificial Synaptic Device with Ultrahigh Neuromorphic Efficacy University of Glasgow, City University of Hong Kong, and Hong Kong Metropolitan University
Thermally Reentrant Crystalline Phase Change in Perovskite-Derivative Nickelate Enabling Reversible Switching of Room-Temperature Electrical Resistivity Tohoku University and University of Tsukuba
Practical hardware for evolvable robots University of York, Edinburgh Napier University, Vrije Universiteit Amsterdam, University of the West of England, and University of Sunderland

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