Chip Industry Technical Paper Roundup: Feb. 13

Advanced packaging roadmap; heterogeneous SoCs; simulation intervals for cache memory; beyond-bound error correction for DRAM; measuring by pixelated STEM and off-axis electron holography; donor qubits in silicon; HW verification assertions via multi-LLMs; single-nm MTJs.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP) SEMI & UCLA
TOP: Towards Open & Predictable Heterogeneous SoCs University of Bologna, ETH Zurich, and UC San Diego
Improving the Representativeness of Simulation Intervals for the Cache Memory System Complutense University of Madrid, imec, and KU Leuven
Unraveling codes: fast, robust, beyond-bound error correction for DRAM Rambus
Measuring electrical properties in semiconductor devices by pixelated STEM and off-axis electron holography (or convergent beams vs. plane waves) CEA-LETI at Universite Grenoble Alpes and EPFL
Superexchange coupling of donor qubits in silicon University of New South Wales
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs Hong Kong University of Science and Technology
Single-nanometer CoFeB/MgO magnetic tunnel junctions with high-retention and high-speed capabilities Tohoku University, Université de Lorraine, and Inamori Research Institute for Science

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