Chip Industry Week In Review


Applied Materials may scale back or cancel its $4 billion new Silicon Valley R&D facility in light of the U.S. government's recent announcement to reduce funding for construction, modernization, or expansion of semiconductor research and development (R&D) facilities in the United States, according to the San Francisco Chronicle. TSMC could receive up to $6.6 billion in direct funding... » read more

High-NA EUVL: Automated Defect Inspection Based on SEMI-SuperYOLO-NAS


A new technical paper titled "Towards Improved Semiconductor Defect Inspection for high-NA EUVL based on SEMI-SuperYOLO-NAS" was published by researchers at KU Leuven, imec, Ghent University, and SCREEN SPE. Abstract "Due to potential pitch reduction, the semiconductor industry is adopting High-NA EUVL technology. However, its low depth of focus presents challenges for High Volume Manufac... » read more

Superconducting Qubits Made Using Industry-Standard, Advanced Semiconductor Manufacturing (imec, KU Leuven)


A new technical paper titled "High-coherence superconducting qubits made using industry-standard, advanced semiconductor manufacturing" was published by researchers at imec and KU Leuven. Abstract: "The development of superconducting qubit technology has shown great potential for the construction of practical quantum computers. As the complexity of quantum processors continues to grow, the ... » read more

Chip Industry Technical Paper Roundup: Feb. 13


New technical papers added to Semiconductor Engineering’s library this week. [table id=197 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


By Jesse Allen, Linda Christensen, and Liz Allan.  The Biden administration plans to invest more than $5B  for semiconductor R&D and workforce support, including in the National Semiconductor Technology Center (NSTC), as part of the rollout of the CHIPS Act. Today's announcement included at least hundreds of millions for the NSTC workforce efforts, including creating a Workforce Cente... » read more

Evaluation of Cache Replacement Policies Using Various Typical Simulation Approaches


A technical paper titled “Improving the Representativeness of Simulation Intervals for the Cache Memory System” was published by researchers at Complutense University of Madrid, imec, and KU Leuven. Abstract: "Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not... » read more

Research Bits: Jan. 2


Synaptic transistor Researchers from Northwestern University, Boston College, and MIT developed a synaptic transistor that simultaneously processes and stores information similar to the human brain. The team said the transistor goes beyond simple machine learning tasks to categorize data and is capable of performing associative learning. The new device is stable at room temperatures. It als... » read more

Technical Paper Roundup: Sept 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=132 /] (more…) » read more

Week In Review: Auto, Security, Pervasive Computing


The U.S. Department of Energy (DOE) announced $15.5 billion in funding and loans for retooling existing automotive factories for the transition to electric vehicles (EVs) and supporting local jobs, plus a notice of intent for $3.5 billion in funding to expand domestic manufacturing of batteries for EVs and the nation’s grid, and for battery materials and components that are currently imported... » read more

Security Research: Technical Paper Round-up


A number of hardware security-related technical papers were presented at the August 2023 USENIX Security Symposium. Here are some highlights with associated links. [table id=130 /] A complete listing of all papers presented at this summer's USENIX conference can be found here and here. The organization provides open access research, and the presentation slides and papers are free to the p... » read more

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