2D materials special issue; measuring direct bonding at wafer scale; information flow for HW; hafnium oxide-based FeFETs for in-memory; fully rubbery Schottky diodes and ICs; layered HW security for cloud and edge; neural architecture and HW accelerator co-design framework.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| Electronic Circuits made of 2D Materials | KAUST & TSMC |
| Double cantilever beam bonding energy measurement using confocal IR microscopy | Univ. Grenoble Alpes, CEA-LETI and SOITEC |
| Quantitative Information Flow for Hardware: Advancing the Attack Landscape | RWTH Aachen University |
| Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications | Fraunhofer IPMS, GlobalFoundries, and TU Bergakademie Freiberg |
| Fully rubbery Schottky diode and integrated devices | Penn State University |
| Hardware-Enabled Security: Enabling a Layered Approach to Platform Security for Cloud and Edge Computing Use Cases | NIST, Intel, AMD, Arm, IBM, Cisco and Scarfone Cybersecurity |
| CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework | Princeton University and Stanford University |
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Related Reading
Technical Paper Library home
Chip Industry’s Technical Paper Roundup: Dec. 5
Optimized chiplet arrangement; verification; FeFET crossbar array; circuit activity fingerprinting; HW trojan threats to chiplets; compiler augmentation; new HW accelerator; connecting quantum with sound; electronic/photonic chip sandwich; Sparseloop in HW accelerator design flows.
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