Chip Industry’s Technical Paper Roundup: Dec. 5

Optimized chiplet arrangement; verification; FeFET crossbar array; circuit activity fingerprinting; HW trojan threats to chiplets; compiler augmentation; new HW accelerator; connecting quantum with sound; electronic/photonic chip sandwich; Sparseloop in HW accelerator design flows.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Demonstration of Multiply-Accumulate Operation With 28 nm FeFET Crossbar Array Fraunhofer IPMS and GlobalFoundries
Circuit Activity Fingerprinting Using Electromagnetic Side-Channel Sensing and Digital Circuit Simulations Georgia Tech
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement ETH Zurich and University of Bologna
Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time MIT
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems Texas A&M University and NYU
On-chip distribution of quantum information using traveling phonons TU Delft, Center for Nanophotonics, AMOLF, and Eindhoven University of Technology
A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators CalTech and University of Southampton
A Formal CHERI-C Semantics for Verification University of Oxford
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling MIT and NVIDIA
Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation MIT (CSAIL), Argonne National Lab, and TU Munich

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Related Reading
Technical Paper Library home
Chip Industry’s Technical Paper Roundup: Nov. 29
Carbon nanotube transistors; XDA Of flip-chip packaged FinFET devices; analog low-dropout voltage regulators; variations in silicon photonic circuits; EV charging cybersecurity; how 2D materials expand; vdW material properties; nanoscale 3D printing; 3D structuring inside GaAs by ULI.

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