Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)


A new technical paper titled “CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework” was published by researchers at Princeton University and Stanford University.

“Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either explore a limited search space or employ suboptimal exploration techniques for simultaneous design decision investigations of the ML model and the accelerator. Furthermore, training the ML model and simulating the accelerator performance is computationally expensive. To address these limitations, this work proposes a novel neural architecture and hardware accelerator co-design framework, called CODEBench. It is composed of two new benchmarking sub-frameworks, CNNBench and AccelBench, which explore expanded design spaces of convolutional neural networks (CNNs) and CNN accelerators,” states the paper.

Find the technical paper here. Published December 2022.

Tuli, Shikhar, et al. “CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework.” ACM Transactions on Embedded Computing Systems (2022).

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