tag: hardware accelerator

Accelerating Zero-Knowledge Proof Generation With Reconfigurable Hardware (KAIST)
By Technical Paper Link - 05 Jun, 2026 - Comments: 0

Researchers from Korea Advanced Institute of Science and Technology (KAIST) have published “ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs”. Abstract “Zero-knowledge proofs (ZKP) allows a prover to convince a verifier of computational correctness without revealing private data, ensuring both privacy and verifiability. However, proof generation i... » read more

Scaling Open-Source HW Accelerator for Deep NN Inference (UDE, Fraunhofer IMS)
By Technical Paper Link - 02 Jun, 2026 - Comments: 0

Researchers from University of Duisburg-Essen and Fraunhofer Institute for Microelectronic Circuits and Systems have published “OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs”. Abstract “The increasing computational complexity of deep neural network inference poses significant challenges for efficient hardware acceleration on embedded platforms, particularly with respect ... » read more

An FPGA-based Accelerator Addressing Bottlenecks in GNN Preprocessing (KAIST et al.)
By Technical Paper Link - 26 Feb, 2026 - Comments: 0

A new technical paper "AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance" was published by researchers at KAIST, Panmnesia, Peking University, Hanyang University, and Pennsylvania State University. Abstract "Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce Au... » read more

Energy-Efficient Signal Detectors For Massive MIMO Using SRAM-Based IMCs (Univ. of Illinois at Urbana–Champaign)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing" was published by researchers at the University of Illinois at Urbana–Champaign. Abstract "This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input mu... » read more

Co-optimizing HW Architecture, Memory Footprint, Device Placement And Per-Chip Operator Scheduling (Georgia Tech, Microsoft)
By Technical Paper Link - 28 Jul, 2024 - Comments: 0

A technical paper titled “Integrated Hardware Architecture and Device Placement Search” was published by researchers at Georgia Institute of Technology and Microsoft Research. Abstract: "Distributed execution of deep learning training involves a dynamic interplay between hardware accelerator architecture and device placement strategy. This is the first work to explore the co-optimization ... » read more

Neuromorphic Hardware Accelerator For Heterogeneous Many-Accelerator SoCs
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip” was published by researchers at Columbia University. Abstract: "Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed wi... » read more

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall
By Technical Paper Link - 01 Aug, 2023 - Comments: 0

A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

A Hardware Accelerator Designed For The Homomorphic SEAL-Embedded Library
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library" was published by researchers at University of Pisa. Abstract: "Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution... » read more

Edge HW-SW Co-Design Platform Integrating RISC-V And HW Accelerators
By Technical Paper Link - 16 May, 2023 - Comments: 0

A new technical paper titled "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" was published by researchers at Columbia University. "We introduce a hardware/software co-design approach that combines software applications designed with Eigen, a powerful open-source C++ library that abstracts linear-algebra workloads, and real-time execution on heterog... » read more

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