Neuromorphic Hardware Accelerator For Heterogeneous Many-Accelerator SoCs

A technical paper titled “SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip” was published by researchers at Columbia University. Abstract: "Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed wi... » read more

Framework for Prototyping And In-Hardware Evaluation of Post-Quantum Cryptography HW Accelerators (TU Darmstadt)

A technical paper titled “PQC-HA: A Framework for Prototyping and In-Hardware Evaluation of Post-Quantum Cryptography Hardware Accelerators” was published by researchers at TU Darmstadt. Abstract: "In the third round of the NIST Post-Quantum Cryptography standardization project, the focus is on optimizing software and hardware implementations of candidate schemes. The winning schemes are ... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall

A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

A Hardware Accelerator Designed For The Homomorphic SEAL-Embedded Library

A technical paper titled "VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library" was published by researchers at University of Pisa. Abstract: "Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution... » read more

Edge HW-SW Co-Design Platform Integrating RISC-V And HW Accelerators

A new technical paper titled "EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators" was published by researchers at Columbia University. "We introduce a hardware/software co-design approach that combines software applications designed with Eigen, a powerful open-source C++ library that abstracts linear-algebra workloads, and real-time execution on heterog... » read more

SW-HW Framework: Graphic Rendering on RISC-V GPUs (Georgia Tech, Cal Poly)

A new technical paper titled "Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs" was published by researchers at Georgia Tech, California Polytechnic State University-San Luis Obispo. Abstract Excerpt: "In this work, we present Skybox, a full-stack open-source GPU architecture with integrated software, compiler, hardware, and simulation environment, that enables end-to-end G... » read more

Hardware Accelerator For Fully Homomorphic Encryption

A technical paper titled "CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data" was published by researchers at MIT, IBM TJ Watson, SRI International, and University of Michigan. "We present CraterLake, the first FHE accelerator that enables FHE programs of unbounded size (i.e., unbounded multiplicative depth). Such computations require very large cipherte... » read more

RISC-V decoupled Vector Processing Unit (VPU) For HPC

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)

A new technical paper titled "CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework" was published by researchers at Princeton University and Stanford University. "Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either... » read more

HW Accelerator Architecture for MI Computation With Low Latency, Energy Efficient (MIT)

A new technical paper titled "Efficient Computation of Map-scale Continuous Mutual Information on Chip in Real Time" was published by researchers at MIT. Find the technical paper here. "In this paper, we introduce a new hardware accelerator architecture for MI computation that features a low-latency, energy-efficient MI compute core and an optimized memory subsystem that provides sufficie... » read more

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