tag: neural networks

Research Bits: Mar. 17
By Jesse Allen - 17 Mar, 2026 - Comments: 0

Photonic ski jumps Researchers from Massachusetts Institute of Technology (MIT), MITRE, University of Arizona, and Sandia National Laboratories developed a new class of photonic devices that enable the precise broadcasting of light from a chip into free space. The chip uses an array of microscopic structures that curl upward, resembling tiny ski jumps, and allows control over how light is e... » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)
By Technical Paper Link - 15 Feb, 2026 - Comments: 0

TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

Hypergraph-based Techniques To Map Spiking Neural Networks on Neuromorphic HW (Politecnico di Milano)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware" was published by researchers at Politecnico di Milano. Abstract "Executing Spiking Neural Networks (SNNs) on neuromorphic hardware poses the problem of mapping neurons to cores. SNNs operate by propagating spikes between neurons that form a graph through synapses. Neuromorphic hardware mimic... » read more

Study Of HW Acceleration for Neural Networks (Arizona State Univ.)
By Technical Paper Link - 02 Jan, 2026 - Comments: 0

A new technical paper titled "Hardware Acceleration for Neural Networks: A Comprehensive Survey" was published by researchers at Arizona State University. Abstract "Neural networks have become a dominant computational workload across cloud and edge platforms, but their rapid growth in model size and deployment diversity has exposed hardware bottlenecks that are increasingly dominated by mem... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security
By Ann Mutschler - 17 Dec, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Next Generation AI: Transitioning Inference From The Cloud To The Edge
By Paul Karazuba - 11 Dec, 2025 - Comments: 0

AI inference deployments are increasingly focused on the edge as manufacturers seek the consistent latency, enhanced privacy, and reduced operational costs they can’t achieve in cloud-based deployments. While cloud-based platforms provide incredible computational power and enable widely adopted services, the dependence on network connectivity inherently creates variability, cost and security ... » read more

Photonic Chip With A 2D Programmable Waveguide (Boston U., UC Irvine, Yale)
By Technical Paper Link - 10 Dec, 2025 - Comments: 0

A new technical paper titled "Arbitrary control over multimode wave propagation for machine learning" was published by researchers at Boston University, UC Irvine, and Yale University. Abstract "Controlled multimode wave propagation can enable more space-efficient photonic processors than architectures based on discrete components connected by single-mode waveguides. Instead of defining d... » read more

Optimizing AI Workloads For Edge Computing
By Ann Mutschler - 03 Dec, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss how some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president an... » read more

LLMs on Analog In-Memory Computing Based Hardware (IBM Research, ETH Zurich)
By Technical Paper Link - 01 Dec, 2025 - Comments: 0

A technical paper titled "Analog Foundation Models" was published by IBM Research– Zurich, ETH Zurich, IBM Research-Almaden, and IBM TJ Watson Research Center. Abstract: "Analog in-memory computing (AIMC) is a promising compute paradigm to improve speed and power efficiency of neural network inference beyond the limits of conventional von Neumann-based architectures. However, AIMC intro... » read more

Comprehensive Performance Bound and Bottleneck Analysis Of Neuromorphic Accelerators (Harvard, Politecnico di Torino, Intel et al.)
By Technical Paper Link - 29 Nov, 2025 - Comments: 0

A new technical paper titled "Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators" was published by researchers at Harvard University, Politecnico di Torino, Intel, LMU Munich, Accenture Labs, BootLoop AI, TU Delft and Wordly. Abstract "Neuromorphic accelerators offer promising platforms for machine learning (ML) inference by leveraging event-driven, spatially-expa... » read more

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