LLM inference HW; scan-based transition fault test; cryogenic ultra-thin body SiGeSn transistor; physical AI at the edge; neuromorphic HW; 2.5D flip-chip packages, thermal-mechanical optimization; gradient electronic landscapes in vdW heterostructures; acoustic side-channel attacks.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Challenges and Research Directions for Large Language Model Inference Hardware | |
| Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set | Purdue University |
| A Cryogenic Ultra-Thin Body SiGeSn Transistor | TU Wien, Johannes Kepler University, Universidad de Granada, Max Planck Institute for Sustainable Materials |
| Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics | Arizona State University |
| Solving sparse finite element problems on neuromorphic hardware | Sandia National Lab |
| Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning | University of Ottawa |
| Gradient Electronic Landscapes in van der Waals Heterostructures | Technical University of Denmark |
| A Survey on Acoustic Side-Channel Attacks: An Artificial Intelligence Perspective | Penn State University |
Find more semiconductor research papers here.
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