Edge neural networks; FeFET security; analog memristor device; sustainable FPGAs; efficient AI memory; nanoscale reconfigurable Si transistors; cryogenic-aware forward body biasing in bulk CMOS; power side-channel against AI accelerators.
New technical papers added to Semiconductor Engineering’s library this week.
| Technical Paper | Research Organizations |
|---|---|
| Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks | Delft University of Technology and Khalifa University |
| MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory | Yale University |
| REFRESH FPGAs: Sustainable FPGA Chiplet Architectures | University of Notre Dame and University of Pittsburgh |
| SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not? | University of Lubeck |
| Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels | TU Wien, CNRS, and University of North Carolina at Chapel Hill |
| Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks | Université Grenoble Alpes, CEA, LETI, and CNRS |
| Embedding security into ferroelectric FET array via in situ memory operation | Pennsylvania State University, University of Notre Dame, Fraunhofer IPMS, National University of Singapore, and North Dakota State University |
| Cryogenic-Aware Forward Body Biasing in Bulk CMOS | QuTech, Tu Delft |
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