Technical Paper Roundup: Sept. 12


New technical papers added to Semiconductor Engineering’s library this week. [table id=51 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Robust Latch Hardened Against QNUs for Safety-Critical Applications in 22nm CMOS Technology


A technical paper titled "Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS" was just published by researchers at Anhui University, Hefei University of Technology, Anhui Polytechnic University, Kyushu Institute of Technology, and the University of Montpellier/CNRS. Abstract: "With the aggressive reduction of CMOS transistor feature sizes, the soft ... » read more

Technical Paper Round-up: July 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=38 /]   Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

Sibyl, a lightweight, reinforcement learning-based data placement technique for hybrid storage systems (ETH Zurich)


New research paper titled "Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning" from researchers at ETH Zurich, Eindhoven University of Technology, and LIRMM, Univ. Montpellier, CNRS. Abstract "Hybrid storage systems (HSS) use multiple different storage devices to provide high and scalable storage capacity at high performance. Recent r... » read more

Technical Paper Round-up: June 14


New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Quantum: Pairing Cooper Pairs Magnifies The Phase Fluctuations of the Ground State


New technical paper titled "Magnifying Quantum Phase Fluctuations with Cooper-Pair Pairing" from researchers at Université PSL, CNRS, Sorbonne Université, Université Paris-Diderot, Inria de Paris, PSL Research University. Abstract "Remarkably, complex assemblies of superconducting wires, electrodes, and Josephson junctions are compactly described by a handful of collective phase degrees ... » read more

Performing Edge Detection With Oscillatory Neural Networks as a Hetero-associative Memory


New research paper titled "Oscillatory Neural Network as Hetero-Associative Memory for Image Edge Detection" from LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier. Abstract "The increasing amount of data to be processed on edge devices, such as cameras, has motivated Artificial Intelligence (AI) integration at the edge. Typical image processing me... » read more

Technical Paper Round-up: May 3


New technical papers added to Semiconductor Engineering’s library this week. [table id=24 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Parallel Circuit Execution & NISQ Computing


Research from LIRMM, University of Montpellier, CNRS. Abstract "Quantum computing is performed on Noisy Intermediate-Scale Quantum (NISQ) hardware in the short term. Only small circuits can be executed reliably on a quantum machine due to the unavoidable noisy quantum operations on NISQ devices, leading to the under-utilization of hardware resources. With the growing demand to access quan... » read more

AI-Based Method to Prune the Design Space of Heterogeneous NoCs


Abstract "Often suffering from under-optimization, Networks-on-Chip (NoCs) heavily impact the efficiency of domain-specific Systems-on-Chip. To cope with this issue, heterogeneous NoCs are promising alternatives. Nevertheless, the design of optimized NoCs satisfying multiple performance objectives is extremely challenging and requires significant expertise. Prior works failed to combine many... » read more

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