Chip Industry Technical Paper Roundup: May 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=227 /] More ReadingTechnical Paper Library home » read more

Framework For Early Anomaly Detection In AMS Components Of Automotive SoCs


A technical paper titled “Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning” was published by researchers at University of Texas at Dallas, Intel Corporation, NXP Semiconductors, and Texas Instruments. Abstract: "Given the widespread use of safety-critical applications in the automotive field, it is crucial to ensure the Functional Safety (FuSa) ... » read more

Chip Industry Technical Paper Roundup: April 30


These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)


A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

Chip Industry Technical Paper Roundup: April 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=214 /] Find last week’s technical paper additions here. » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)


A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)


A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

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