Survey of CXL Implementations and Standards (Intel, Microsoft)


A new technical paper titled "An Introduction to the Compute Express Link (CXL) Interconnect" was published by researchers at Intel Corporation, Microsoft, and University of Washington. Abstract "The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-... » read more

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)


A technical paper titled “Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution” was published by researchers at ETH Zürich and Intel Corporation.  This paper earned the Best Paper Award in the International Symposium on Computer Architecture (ISCA). Abstract: "Load instructions often limit instruction-level parallelism (ILP) in modern pr... » read more

Chip Industry Technical Paper Roundup: July 22


New technical papers recently added to Semiconductor Engineering’s library. [table id=245 /] More ReadingTechnical Paper Library home » read more

Chip Industry Technical Paper Roundup: July 16


New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home   » read more

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)


A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Manual RTL design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath des... » read more

Chip Industry Week In Review


The Design Automation Conference morphed into the Chips to Systems Conference, reflecting an industry shift from monolithic SoCs to assemblies of chiplets in various flavors of advanced packaging. The change drew a slew of students and a resurgent buzz, fueled by discussions about heterogeneous integration, reliability, and ways to leverage AI/ML to speed up design and verification processes. ... » read more

Chip Industry Technical Paper Roundup: June 25


New technical papers recently added to Semiconductor Engineering’s library. [table id=236 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development. Onsemi plans to build a $2 billion silicon carbide production plant in the ... » read more

Plasma Etching : Challenges And Options Going Forward (UMD, IBM, Lam Research, Intel, Samsung et al.)


A new technical paper titled "Future of plasma etching for microelectronics: Challenges and opportunities" was published by researchers from numerous academic institutions and companies, including University of Maryland, IBM, Arkema, UCLA, Lam Research, Intel Corporation, Samsung, Air Liquide, Sony, and many others. Abstract: "Plasma etching is an essential semiconductor manufacturing techn... » read more

Chip Industry Technical Paper Roundup: May 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=227 /] More ReadingTechnical Paper Library home » read more

← Older posts