Chip Industry Week In Review


BAE Systems and GlobalFoundries are teaming up to strengthen the supply of chips for national security programs, aligning technology roadmaps and collaborating on innovation and manufacturing. Focus areas include advanced packaging, GaN-on-silicon chips, silicon photonics, and advanced technology process development. Onsemi plans to build a $2 billion silicon carbide production plant in the ... » read more

Plasma Etching : Challenges And Options Going Forward (UMD, IBM, Lam Research, Intel, Samsung et al.)


A new technical paper titled "Future of plasma etching for microelectronics: Challenges and opportunities" was published by researchers from numerous academic institutions and companies, including University of Maryland, IBM, Arkema, UCLA, Lam Research, Intel Corporation, Samsung, Air Liquide, Sony, and many others. Abstract: "Plasma etching is an essential semiconductor manufacturing techn... » read more

Chip Industry Technical Paper Roundup: May 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=227 /] More ReadingTechnical Paper Library home » read more

Framework For Early Anomaly Detection In AMS Components Of Automotive SoCs


A technical paper titled “Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning” was published by researchers at University of Texas at Dallas, Intel Corporation, NXP Semiconductors, and Texas Instruments. Abstract: "Given the widespread use of safety-critical applications in the automotive field, it is crucial to ensure the Functional Safety (FuSa) ... » read more

Chip Industry Technical Paper Roundup: April 30


These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)


A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

Chip Industry Technical Paper Roundup: April 8


New technical papers recently added to Semiconductor Engineering’s library. [table id=214 /] Find last week’s technical paper additions here. » read more

Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)


A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

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