MIT’s AI accelerators and processors survey; SOT-based MRAM design at 7nm; in-DRAM TRNG using simultaneous multiple-row activation; chiplet-locality for memory mapping; FeRAM vs. DRAM performance; 180 automotive SoC vulnerabilities; EUV + DSA progress; multimodal chip physical design engineer assistant.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Lincoln AI Computing Survey (LAICS) and Trends: Survey On Accelerators and Processors for Inference, With Peak Performance And Power Comparisons | MIT Lincoln Laboratory Supercomputing Center |
| Comprehensive device to system co-design for SOT-MRAM at the 7nm node | Georgia Institute of Technology, Intel |
| In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips | ETH Zurich, CISPA |
| Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs | Electronics and Telecommunications Research Institute (ETRI), Sungkyunkwan University |
| Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model | Georgia Tech, imec, National Technical University of Athens |
| An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software | Chalmers University of Technology, University of Gothenburg |
| Directed self-assembly of block copolymers for high-precision patterning in the era of extreme ultraviolet lithography | University of Chicago, Lawrence Berkeley National Laboratory, Argonne National Laboratory |
| Multimodal Chip Physical Design Engineer Assistant | National Taiwan University, UCLA, NVIDIA Research |
Find more semiconductor research papers here.
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