Chip Industry Week In Review


Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Chip Industry Week In Review


Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

Chip Industry Technical Paper Roundup: Feb. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=525 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

Chip Industry Week in Review


Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still. Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i... » read more

HW-Triggered Backdoors Across Common GPU Accelerators (BIFOLD, TU Berlin, CISPA)


A new technical paper titled "Hardware-Triggered Backdoors" was published by researchers at Berlin Institute for the Foundations of Learning and Data (BIFOLD), TU Berlin and CISPA Helmholtz Center for Information Security. Abstract "Machine learning models are routinely deployed on a wide range of computing hardware. Although such hardware is typically expected to produce identical result... » read more

Chip Industry Technical Paper Roundup: Nov. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=488 /] Find more semiconductor research papers here. » read more

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)


A new technical paper titled "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips" was published by researchers at ETH Zürich and CISPA. Abstract "In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chi... » read more

Chip Industry Technical Paper Roundup: Oct. 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=486 /] Find more semiconductor research papers here. » read more

Understanding and Mitigating Column-Based Read Disturbance in DRAM Chips (ETH Zurich, CISPA)


A new technical paper titled "ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems" was published by researchers at ETH Zurich and CISPA. Abstract "We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) ope... » read more

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