Chip Industry Technical Paper Roundup: Nov. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=488 /] Find more semiconductor research papers here. » read more

Multimodal LLM Assistant for Chip Physical Design (National Taiwan Univ., UCLA, NVIDIA)


A new technical paper titled "Multimodal Chip Physical Design Engineer Assistant" was published by researchers at National Taiwan University, University of California, Los Angeles and NVIDIA Research. Abstract "Modern chip physical design relies heavily on Electronic Design Automation (EDA) tools, which often struggle to provide interpretable feedback or actionable guidance for improving ro... » read more

LLM Inference: Core Bottlenecks Imposed By Memory, Compute Capacity, Synchronization Overheads (NVIDIA)


A new technical paper titled "Efficient LLM Inference: Bandwidth, Compute, Synchronization, and Capacity are all you need" was published by NVIDIA. Abstract "This paper presents a limit study of transformer-based large language model (LLM) inference, focusing on the fundamental performance bottlenecks imposed by memory bandwidth, memory capacity, and synchronization overhead in distributed ... » read more

Processing-Using-DRAM: Attaining High-Performance Via Dynamic Precision Bit-Serial Arithmetic (ETH Zurich, et al.)


A new technical paper titled "Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic" was published by researchers at ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research. Abstract "Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM structures ... » read more